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efm32 pearl gecko family efm32pg1 data sheet the efm32 pearl gecko mcus are the worlds most energy- friendly microcontrollers. efm32pg1 features a powerful 32-bit arm ? cortex ? -m4 and a wide selection of periph- erals, including a unique cryptographic hardware engine supporting aes, ecc, and sha. these features, combined with ultra-low current active mode and short wake-up time from energy-saving modes, make efm32pg1 microcontrollers well suited for any battery-powered application, as well as other systems requiring high performance and low-energy consumption. example applications: energy friendly features ? arm cortex-m4 at 40 mhz ? ultra low energy operation: ? 1.1 a em3 stop current (cryotimer running with state/ram retention) ? 1.4 a em2 deepsleep current (rtcc running with state and ram retention) ? 60 a/mhz in energy mode 0 (em0) ? hardware cryptographic engine supports aes, ecc, and sha ? integrated dc-dc converter ? cryotimer operates down to em4 ? 5 v tolerant i/o ? iot devices and sensors ? health and fitness ? smart accessories ? home automation and security ? industrial and factory automation peripheral reflex system 32-bit bus core / memory arm cortex tm m4 processor with dsp extensions and fpu timers and triggers cryotimer real time counter and calendar timer/counter low energy timer pulse counter watchdog timer lowest power mode with peripheral operational: em3 - stop em2 C deep sleep em1 - sleep em4 - hibernate em4 - shutoff em0 - active analog interfaces adc idac analog comparator energy management brown-out detector dc-dc converter voltage regulator voltage monitor power-on reset other crypto crc clock management high frequency crystal oscillator low frequency crystal oscillator low frequency rc oscillator high frequency rc oscillator ultra low frequency rc oscillator auxiliary high frequency rc oscillator flash program memory ram memory debug interface dma controller serial interfaces usart low energy uart tm i 2 c i/o ports external interrupts general purpose i/o pin reset pin wakeup memory protection unit silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 this information applies to a product under development. its characteristics and specifications are subject to change without notice.
1. feature list the efm32pg1 highlighted features are listed below. ? arm cortex-m4 cpu platform ? high performance 32-bit processor @ up to 40 mhz ? wake-up interrupt controller ? flexible energy management system ? 60 a/mhz in energy mode 0 (em0) ? 1.4 a em2 deepsleep current (rtcc running with state and ram retention) ? 1.1 a em3 stop current (cryotimer running with state/ram retention) ? up to 256 kb flash program memory ? 32 kb ram data memory ? up to 32 general purpose i/o pins ? configurable push-pull, open-drain, pull-up/down, input fil- ter, drive strength ? configurable peripheral i/o locations ? asynchronous external interrupts ? output state retention and wake-up from shutoff mode ? hardware cryptography ? aes 128/256-bit keys ? ecc b/k163, b/k233, p192, p224, p256 ? sha-1 and sha-2 (sha-224 and sha-256) ? timers/counters ? 2 16-bit timer/counter ? 3 + 4 compare/capture/pwm channels ? 1 32-bit real time counter and calendar ? 1 32-bit ultra low energy cryotimer for periodic wake- up from any energy mode ? 16-bit low energy timer for waveform generation ? 16-bit pulse counter with asynchronous operation ? watchdog timer with dedicated rc oscillator @ 50 na ? 8 channel dma controller ? 12 channel peripheral reflex system (prs) for autono- mous inter-peripheral signaling ? communication interfaces ? 2 universal synchronous/asynchronous receiver/ trans- mitter ? uart/spi/smartcard (iso 7816)/irda/i2s/lin ? triple buffered full/half-duplex operation with flow control ? low energy uart ? autonomous operation with dma in deep sleep mode ? i 2 c interface with smbus support ? address recognition in em3 stop mode ? ultra low-power precision analog peripherals ? 12-bit 1 msamples/s analog to digital converter ? 2 analog comparator ? digital to analog current converter ? up to 24 pins connected to analog channels (aport) shared between analog comparators, adc, and idac ? ultra efficient power-on reset and brown-out detector ? debug interface ? 2-pin serial wire debug interface ? 1-pin serial wire viewer ? jtag (programming only) ? pre-programmed uart bootloader ? wide operating range ? 1.85 v to 3.8 v single power supply ? integrated dc-dc, down to 1.8 v output with up to 200 ma load current for system ? temperature range -40 to 85 oc ? packages ? 7 mm 7 mm qfn48 ? 5 mm 5 mm qfn32 efm32pg1 data sheet feature list silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 1
2. ordering information ordering code flash (kb) ram (kb) dc-dc converter gpio package efm32pg1b200f256gm48-b0 * 256 32 yes 32 qfn48 efm32pg1b200f128gm48-b0 * 128 32 yes 32 qfn48 EFM32PG1B200F256GM32-B0 * 256 32 yes 20 qfn32 efm32pg1b200f128gm32-b0 * 128 32 yes 20 qfn32 efm32pg1b100f256gm32-b0 * 256 32 no 24 qfn32 efm32pg1b100f128gm32-b0 * 128 32 no 24 qfn32 * engineering samples efm32 C 1 b f g b0 r tape and reel (optional) revision pin count package C m (qfn) flash memory size in kb memory type (flash) feature set code g j 200 256 m 32 temperature grade C g (-40 to +85 c), i (-40 to +125 c) performance grade C p (performance), b (basic), v (value) family C j (jade), p (pearl) generation energy friendly microcontroller 32-bit gecko figure 2.1. opn decoder efm32pg1 data sheet ordering information silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 2
3. system overview 3.1 introduction the efm32pg1 product family is well suited for any battery operated application as well as other systems requiring high performance and low energy consumption. this section gives a short introduction to the mcu system. the detailed functional description can be found in the efm32pg1 reference manual. a block diagram of the efm32pg1 family is shown in figure 3.1 detailed efm32pg1 block diagram on page 3 . the diagram shows a superset of features available on the family, which vary by opn. for more information about specific device features, consult order- ing information . clock configuration analog peripherals lfxtal_p lfxtal_n lfxo idac arm cortex-m4 core up to 256 kb isp flash program memory up to 32 kb ram a h b watchdog timer dc-dc converter dvdd reset management unit voltage monitor / brown out detector resetn reset debug / programming hardware digital peripherals input mux port mapper port i/o configuration i2c analog comparator 12-bit adc temp sensor vref vdd vdd internal reference timer cryotimer pcnt usart port a drivers port b drivers pan port c drivers pcn pbn port d drivers pdn letimer rtc / rtcc iovdd auxhfrco hfrco ulfrco hfxo port f drivers pfn serial wire memory protection unit lfrco a p b leuart crypto crc dma controller + - aport power net vregvdd vss vregvss vregsw bypass hfxtal_p hfxtal_n figure 3.1. detailed efm32pg1 block diagram efm32pg1 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 3
3.2 power the efm32pg1 has an energy management unit (emu) and efficient integrated regulators to generate internal supply voltages. only a single external supply voltage is required, from which all internal voltages are created. an optional integrated dc-dc buck regulator can be utilized to further reduce the current consumption. the dc-dc regulator requires one external inductor and one external capacitor. avdd and vregvdd need to be 1.85 v or higher for the mcu to operate across all conditions; however the rest of the system will operate down to 1.62 v, including the digital supply and i/o. this means that the device is fully compatible with 1.8 v components. running from a sufficiently high supply, the device can use the dc-dc to regulate voltage not only for itself, but also for other pcb com- ponents, supplying up to a total of 200 ma. 3.2.1 energy management unit (emu) the energy management unit manages transitions of energy modes in the device. each energy mode defines which peripherals and features are available and the amount of current the device consumes. the emu can also be used to turn off the power to unused ram blocks, and it contains control registers for the dc-dc regulator and the voltage monitor (vmon). the vmon is used to monitor multiple supply voltages. it has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen below a chosen threshold. 3.2.2 dc-dc converter the dc-dc buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes em0, em1, em2 and em3, and can supply up to 200 ma to the device and surrounding pcb components. protection features include programmable current limiting, short-circuit protection, and dead-time protection. the dc-dc converter may also enter bypass mode when the input volt- age is too low for efficient operation. in bypass mode, the dc-dc input supply is internally connected directly to its output through a low resistance switch. bypass mode also supports in-rush current limiting to avoid dipping the input supply due to excessive current transi- ents. 3.3 general purpose input/output (gpio) efm32pg1 has up to 32 general purpose input/output pins. each gpio pin can be individually configured as either an output or input. more advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual gpio pin. the gpio pins can be overridden by peripheral connections, like spi communication. each peripheral connection can be routed to sev- eral gpio pins on the device. the input value of a gpio pin can be routed through the peripheral reflex system to other peripherals. the gpio subsystem supports asynchronous external pin interrupts. 3.4 clocking 3.4.1 clock management unit (cmu) the clock management unit controls oscillators and clocks in the efm32pg1 . individual enabling and disabling of clocks to all periph- eral modules is perfomed by the cmu. the cmu also controls enabling and configuration of the oscillators. a high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators. 3.4.2 internal and external oscillators the efm32pg1 supports two crystal oscillators and fully integrates four rc oscillators, listed below. ? a high frequency crystal oscillator (hfxo) with integrated load capacitors, tunable in small steps, provides a precise timing refer- ence for the mcu. crystal frequencies in the range from 38 to 40 mhz are supported. an external clock source such as a tcxo can also be applied to the hfxo input for improved accuracy over temperature. ? a 32.768 khz crystal oscillator (lfxo) provides an accurate timing reference for low energy modes. ? an integrated high frequency rc oscillator (hfrco) is available for the mcu system, when crystal accuracy is not required. the hfrco employs fast startup at minimal energy consumption combined with a wide frequency range. ? an integrated auxilliary high frequency rc oscillator (auxhfrco) is available for timing the general-purpose adc and the serial wire debug port with a wide frequency range. ? an integrated low frequency 32.768 khz rc oscillator (lfrco) can be used as a timing reference in low energy modes, when crys- tal accuracy is not required. ? an integrated ultra-low frequency 1 khz rc oscillator (ulfrco) is available to provide a timing reference at the lowest energy con- sumption in low energy modes. efm32pg1 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 4
3.5 counters/timers and pwm 3.5.1 timer/counter (timer) timer peripherals keep track of timing, count events, generate pwm outputs and trigger timed actions in other peripherals through the prs system. the core of each timer is a 16-bit counter with up to 4 compare/capture channels. each channel is configurable in one of three modes. in capture mode, the counter state is stored in a buffer at a selected input event. in compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. in pwm mode, the timer supports generation of pulse-width modulation (pwm) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit timer_0 only. 3.5.2 real time counter and calendar (rtcc) the real time counter and calendar (rtcc) is a 32-bit counter providing timekeeping in all energy modes. the rtcc includes a binary coded decimal (bcd) calendar mode for easy time and date keeping. the rtcc can be clocked by any of the on-board oscilla- tors with the exception of the auxhfrco, and it is capable of providing system wake-up at user defined instances. when receiving frames, the rtcc value can be used for timestamping. the rtcc includes 128 bytes of general purpose data retention, allowing easy and convenient data storage in all energy modes. 3.5.3 low energy timer (letimer) the unique letimer is a 16-bit timer that is available in energy mode em2 deep sleep in addition to em1 sleep and em0 active. this allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. the letimer can be used to output a variety of wave- forms with minimal software intervention. the letimer is connected to the real time counter and calendar (rtcc), and can be con- figured to start counting on compare matches from the rtcc. 3.5.4 ultra low power wake-up timer (cryotimer) the cryotimer is a 32-bit counter that is capable of running in all energy modes. it can be clocked by either the 32.768 khz crystal oscillator (lfxo), the 32.768 khz rc oscillator (lfrco), or the 1 khz rc oscillator (ulfrco). it can provide periodic wakeup events and prs signals which can be used to wake up peripherals from any energy mode. the cryotimer provides a wide range of inter- rupt periods, facilitating flexible ultra-low energy operation. 3.5.5 pulse counter (pcnt) the pulse counter (pcnt) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. the clock for pcnt is selectable from either an external source on pin pctnn_s0in or from an internal timing reference, selectable from among any of the internal oscillators, except the auxhfrco. the module may operate in energy mode em0 active, em1 sleep, em2 deep sleep, and em3 stop. 3.5.6 watchdog timer (wdog) the watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the cpu clock. it has windowed monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. the watchdog can also monitor autonomous systems driven by prs. 3.6 communications and other digital peripherals 3.6.1 universal synchronous/asynchronous receiver/transmitter (usart) the universal synchronous/asynchronous receiver/transmitter is a flexible serial i/o module. it supports full duplex asynchronous uart communication with hardware flow control as well as rs-485, spi, microwire and 3-wire. it can also interface with devices sup- porting: ? iso7816 smartcards ? irda ? i 2 s efm32pg1 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 5
3.6.2 low energy universal asynchronous receiver/transmitter (leuart) the unique leuart tm provides two-way uart communication on a strict power budget. only a 32.768 khz clock is needed to allow uart communication up to 9600 baud. the leuart includes all necessary hardware to make asynchronous serial communication possible with a minimum of software intervention and energy consumption. 3.6.3 inter-integrated circuit interface (i 2 c) the i 2 c module provides an interface between the mcu and a serial i 2 c bus. it is capable of acting as both a master and a slave and supports multi-master buses. standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10 kbit/s up to 1 mbit/s. slave arbitration and timeouts are also available, allowing implementation of an smbus-compliant system. the interface provided to software by the i 2 c module allows precise timing control of the transmission process and highly automated trans- fers. automatic recognition of slave addresses is provided in active and low energy modes. 3.6.4 peripheral reflex system (prs) the peripheral reflex system provides a communication network between different peripheral modules without software involvement. peripheral modules producing reflex signals are called producers. the prs routes reflex signals from producers to consumer periph- erals which in turn perform actions in response. edge triggers and other functionality can be applied by the prs. the prs allows pe- ripheral to act autonomously without waking the mcu core, saving power. 3.7 security features 3.7.1 gpcrc (general purpose cyclic redundancy check) the gpcrc module implements a cyclic redundancy check (crc) function. it supports both 32-bit and 16-bit polynomials. the sup- ported 32-bit polynomial is 0x04c11db7 (ieee 802.3), while the 16-bit polynomial can be programmed to any value, depending on the needs of the application. common 16-bit polynomials are 0x1021 (ccitt-16), and 0x8005 (802.15.4, and usb). 3.7.2 crypto accelerator (crypto) the crypto accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. efm32pg1 devices support aes encryption and decryption with 128- or 256-bit keys, ecc over both gf(p) and gf(2 m ), and sha-1 and sha-2 (sha-224 and sha-256). supported modes of operation for aes include: ecb, ctr, cbc, pcbc, cfb, ofb, cbc-mac, gmac and ccm. supported ecc nist recommended curves include p-192, p-224, p-256, k-163, k-233, b-163 and b-233. the crypto module allows fast processing of gcm (aes), ecc and sha with little cpu intervention. crypto also provides trigger signals for dma read and write operations. 3.8 analog 3.8.1 analog port (aport) the analog port (aport) is an analog interconnect matrix allowing access to analog modules adc, acmp, and idac on a flexible selection of pins. each aport bus consists of analog switches connected to a common wire. since many clients can operate differen- tially, buses are grouped by x/y pairs. 3.8.2 analog comparator (acmp) the analog comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high- er. inputs are selected from among internal references and external pins. the tradeoff between response time and current consumption is configurable by software. two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. the acmp can also be used to monitor the supply voltage. an interrupt can be generated when the supply falls below or rises above the programmable threshold. efm32pg1 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 6
3.8.3 analog to digital converter (adc) the adc is a successive approximation register (sar) architecture, with a resolution of up to 12 bits at up to 1 msamples/s. the output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples. the adc includes integrated voltage references and an integrated temperature sensor. inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential. 3.8.4 digital to analog current converter (idac) the digital to analog current converter can source or sink a configurable constant current. this current can be driven on an output pin or routed to the selected adc input pin for capacitive sensing. the current is programmable between 0.05 a and 64 a with several ranges with various step sizes. 3.9 reset management unit (rmu) the rmu is responsible for handling reset of the efm32pg1 . a wide range of reset sources are available, including several power supply monitors, pin reset, software controlled reset, core lockup reset and watchdog reset. 3.10 core and memory 3.10.1 processor core the arm cortex-m processor includes a 32-bit risc processor integrating the following features and tasks in the system: ? arm cortex-m4 risc processor achieving 1.25 dhrystone mips/mhz ? memory protection unit (mpu) supporting up to 8 memory segments ? up to 256 kb flash program memory ? up to 32 kb ram data memory ? configuration and event handling of all modules ? 2-pin serial-wire debug interface 3.10.2 memory system controller (msc) the memory system controller (msc) is the program memory unit of the microcontroller. the flash memory is readable and writable from both the cortex-m and dma. the flash memory is divided into two blocks; the main block and the information block. program code is normally written to the main block, whereas the information block is available for special user data and flash lock bits. there is also a read-only page in the information block containing system and device calibration data. read and write operations are supported in en- ergy modes em0 active and em1 sleep. 3.10.3 linked direct memory access controller (ldma) the linked direct memory access (ldma) controller features 8 channels capable of performing memory operations independently of software. this reduces both energy consumption and software workload. the ldma allows operations to be linked together and stag- ed, enabling sophisticated operations to be implemented. efm32pg1 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 7
3.11 memory map the efm32pg1 memory map is shown in the figures below. ram and flash sizes are for the largest memory configuration. figure 3.2. efm32pg1 memory map core peripherals and code space efm32pg1 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 8
figure 3.3. efm32pg1 memory map peripherals 3.12 configuration summary the features of the efm32pg1 are a subset of the feature set described in the device reference manual. the table below describes device specific implementation of the features. remaining modules support full configuration. table 3.1. configuration summary module configuration pin connections usart0 irda smartcard us0_tx, us0_rx, us0_clk, us0_cs usart1 irda i 2 s smartcard us1_tx, us1_rx, us1_clk, us1_cs timer0 with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 tim1_cc[3:0] efm32pg1 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 9
4. electrical specifications 4.1 electrical characteristics all electrical parameters in all tables are specified under the following conditions, unless stated otherwise: ? typical values are based on t amb =25 c and v dd = 3.3 v, by production test and/or technology characterization. ? minimum and maximum values represent the worst conditions of ambient temperature, supply voltage, and process variation. refer to table 4.2 general operating conditions on page 11 for more details about operational supply and temperature limits. 4.1.1 absolute maximum ratings stresses above those listed below may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. for more information on the available quality and relia- bility data, see the quality and reliability monitor report at http://www.silabs.com/support/quality/pages/default.aspx . table 4.1. absolute maximum ratings parameter symbol test condition min typ max unit storage temperature range t stg -50 - 150 c external main supply voltage v ddmax 0 - 3.8 v external main supply voltage ramp rate v ddrampmax - - 1 v / s voltage on any 5v tolerant gpio pin 1 v digpin -0.3 - min of 5.25 and iovdd +2 v voltage on non-5v tolerant gpio pins -0.3 - iovdd+0.3 v voltage on hfxo pins v hfxopin -0.3 - 1.4 v total current into v ss ground lines (sink) i vssmax - - tbd ma current per i/o pin (sink) i iomax - - 50 ma current per i/o pin (source) - - 50 ma current for all i/o pins (sink) i ioallmax - - tbd ma current for all i/o pins (source) - - tbd ma voltage difference between avdd and vregvdd v dd - - 0.3 v note: 1. when a gpio pin is routed to the analog module through the aport, the maximum voltage = iovdd. efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 10
4.1.2 operating conditions when assigning supply sources, the following requirements must be observed: ? vregvdd must be the highest voltage in the system ? vregvdd = avdd_n ? dvdd avdd_n ? iovdd avdd_n 4.1.2.1 general operating conditions table 4.2. general operating conditions parameter symbol test condition min typ max unit ambient temperature range t amb -40 25 85 c avdd supply voltage 1 v avdd 1.85 3.3 3.8 v vregvdd operating supply voltage 12 v vregvdd dcdc in regulation 2.4 3.3 3.8 v dcdc in bypass 50ma load tbd 3.3 3.8 v dcdc not in use. dvdd external- ly shorted to vregvdd 1.85 3.3 3.8 v dvdd operating supply volt- age v dvdd 1.62 - v vregvdd v iovdd operating supply voltage v iovdd 1.62 - v vregvdd v difference between avdd and vregvdd, abs(avdd- vregvdd) dv dd - - 0.1 v hfclk frequency f core 0 wait-states (mode = ws0) 3 - - 26 mhz 1 wait-states (mode = ws1) 3 - 38.4 40 mhz note: 1. vregvdd must be tied to avdd. both vregvdd and avdd minimum voltages must be satisfied for the part to operate. 2. the minimum voltage required in bypass mode is calculated using r byp from the dcdc specification table. requirements for other loads can be calculated as v dvdd_min +i load * r byp_max 3. in msc_readctrl register efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 11
4.1.3 dc-dc converter test conditions: l dcdc =4.7 h, c dcdc =1.0 f, v dcdc_i =3.3 v, v dcdc_o =1.8 v, i dcdc_load =50 ma, heavy drive configuration, f dcdc_ln =8 mhz, unless otherwise indicated. table 4.3. dc-dc converter parameter symbol test condition min typ max unit input voltage range v dcdc_i bypass mode tbd - 3.8 v low noise (ln) or low power (lp) mode, 1.8 v output, 200 ma load current 2.4 - 3.8 v output voltage range v dcdc_o 1.8v configuration 1.8 - - v steady-state output ripple v r esr=50 ?, esl=2 nh on 1 f fil- ter cap. - 3 - mvpp output voltage under/over- shoot v ov ccm mode (lnforceccm 1 = 1), load changes between 0 ma and 100 ma - 100 - mv dcm mode (lnforceccm 1 = 0), load changes between 0 ma and 10 ma - 150 - mv dc line regulation v reg input changes between 3.8 v and 2.4 v - 0.1 - % dc load regulation i reg load changes between 0 ma and 100 ma in ccm mode - 0.1 - % quiescent current i dcdc_q low power (lp) mode, lowest bias setting (lpcmpbias 1 = bias0) - 50 - na low noise (ln) mode, dcm con- figuration (lnforceccm 1 = 0) - 0.3 - ma low noise (ln) mode, ccm con- figuration (lnforceccm 1 = 1) - 0.8 - ma regulation dc accuracy acc dc low noise (ln) mode, 1.8 v target output tbd - - mv low power (lp) mode, lpcmpbias 1 = 0, 1.8 v target output tbd - mv low power (lp) mode, lpcmpbias 1 = 3, 1.8 v target output tbd - mv max load current i load_max low noise (ln) mode - 200 ma low power (lp) mode, lpcmpbias 1 = 3 - 10 ma efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 12
parameter symbol test condition min typ max unit capacitance of dcdc output capacitor c dcdc 1 - 10 f inductance of dcdc output inductor l dcdc - 4.7 - h resistance in bypass mode r byp tbd 0.8 tbd ? peak current limit range i ipk 20 - 640 ma peak current limit step i pk_step light drive 2 - 20 - ma medium drive 2 - 40 - ma heavy drive 2 - 80 - ma note: 1. in emu_dcdcmiscctrl register 2. drive levels are defined by configuration of the pslicesel and nslicesel registers. light drive: pslicesel=nslicesel=3; medium drive: pslicesel=nslicesel=7; heavy drive: pslicesel=nslicesel=15. efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 13
4.1.4 current consumption 4.1.4.1 current consumption 1.85v without dc/dc table 4.4. current consumption 1.85v without dc/dc parameter symbol test condition min typ max unit current consumption in em0 active mode, all peripherals disabled i active 38.4 mhz crystal, cpu running while loop from flash - 128 - a/mhz 38 mhz hfrco, cpu running prime from flash - 87 - a/mhz 38 mhz hfrco, cpu running while loop from flash - 103 - a/mhz 38 mhz hfrco, cpu running coremark from flash - 112 - a/mhz 26 mhz hfrco, cpu running while loop from flash - 105 - a/mhz 1 mhz hfrco, cpu running while loop from flash - 235 - a/mhz current consumption in em1 sleep mode. all peripherals disabled i em1 38.4 mhz crystal - 61 - a/mhz 38 mhz hfrco - 35 - a/mhz 26 mhz hfrco - 37 - a/mhz 1 mhz hfrco - 167 - a/mhz current consumption in em2 deep sleep mode. i em2 full ram retention and rtcc running from lfxo - 3.36 - a 4 kb ram retention and rtcc running from lfrco - 3.13 - a current consumption in em3 stop mode i em3 full ram retention and cryo- timer running from ulfrco - 2.84 - a current consumption in em4h hibernate mode i em4 128 byte ram retention, rtcc running from lfxo - 1.08 - a 128 byte ram retention, cryo- timer running from ulfrco - 0.64 - a 128 byte ram retention, no rtcc - 0.63 - a current consumption in em4s shutoff mode i em4s no ram retention, no rtcc - 0.02 - a efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 14
4.1.4.2 current consumption 3.3v without dc/dc table 4.5. current consumption 3.3v without dc/dc parameter symbol test condition min typ max unit current consumption in em0 active mode, all peripherals disabled i active 38.4 mhz crystal, cpu running while loop from flash - 129 - a/mhz 38 mhz hfrco, cpu running prime from flash - 87 - a/mhz 38 mhz hfrco, cpu running while loop from flash - 103 - a/mhz 38 mhz hfrco, cpu running coremark from flash - 112 - a/mhz 26 mhz hfrco, cpu running while loop from flash - 105 - a/mhz 1 mhz hfrco, cpu running while loop from flash - 237 - a/mhz current consumption in em1 sleep mode. all peripherals disabled i em1 38.4 mhz crystal - 61 - a/mhz 38 mhz hfrco - 35 - a/mhz 26 mhz hfrco - 37 - a/mhz 1 mhz hfrco - 170 - a/mhz current consumption in em2 deep sleep mode. i em2 full ram retention and rtcc running from lfxo - 3.47 - a 4 kb ram retention and rtcc running from lfrco - 3.35 - a current consumption in em3 stop mode i em3 full ram retention and cryo- timer running from ulfrco - 2.92 - a current consumption in em4h hibernate mode i em4 128 byte ram retention, rtcc running from lfxo - 1.13 - a 128 byte ram retention, cryo- timer running from ulfrco - 0.67 - a 128 byte ram retention, no rtcc - 0.66 - a current consumption in em4s shutoff mode i em4s no ram retention, no rtcc - 0.04 - a efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 15
4.1.4.3 current consumption 3.3v with dc/dc table 4.6. current consumption 3.3v with dc/dc parameter symbol test condition min typ max unit current consumption in em0 active mode. all peripherals disabled, dcdc in lownoise mode i active 38.4 mhz crystal, cpu running while loop from flash. - 87 - a/mhz 38 mhz hfrco, cpu running prime from flash - 63 - a/mhz 38 mhz hfrco, cpu running while loop from flash - 72 - a/mhz 38 mhz hfrco, cpu running coremark from flash - 78 - a/mhz 26 mhz hfrco, cpu running while loop from flash - 79 - a/mhz current consumption in em1 sleep mode. all peripherals disabled, dcdc in lowpow- er mode. i em1 38.4 mhz crystal - 39 - a/mhz 38 mhz hfrco - 23 - a/mhz 26 mhz hfrco - 25 - a/mhz 1 mhz hfrco - 142 - a/mhz current consumption in em2 deep sleep mode. i em2 full ram retention and rtcc running from lfxo - 1.4 - a 4 kb ram retention and rtcc running from lfrco - 1.4 - a current consumption in em3 stop mode i em3 full ram retention and cryo- timer running from ulfrco - 1.1 - a current consumption in em4h hibernate mode i em4 128 byte ram retention, rtcc running from lfxo - 0.9 - a 128 byte ram retention, cryo- timer running from ulfrco - 0.6 - a 128 byte ram retention, no rtcc - 0.6 - a current consumption in em4s shutoff mode i em4s no ram retention, no rtcc - 0.03 - a efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 16
4.1.5 wake up times table 4.7. wake up times parameter symbol test condition min typ max unit wake up from em2 deep sleep t em2_wu code execution from flash - 10.7 - s code execution from ram - 3 - s wake up from em3 stop t em3_wu executing from flash - 10.7 - s executing from ram - 3 - s wake up from em4h hiber- nate 1 t em4h_wu executing from flash - 60 - s wake up from em4s shut- off 1 t em4s_wu - 290 - s note: 1. time from wakeup request until first instruction is executed. wakeup results in device reset. 4.1.6 brown out detector table 4.8. brown out detector parameter symbol test condition min typ max unit dvddbod threshold v dvddbod dvdd rising - - tbd v dvdd falling tbd - - v dvdd bod hysteresis v dvddbod_hyst - 24 - mv dvdd response time t dvddbod_delay supply drops at 0.1v/s rate - 2.4 - s avdd bod threshold v avddbod avdd rising - - 1.85 v avdd falling tbd - - v avdd bod hysteresis v avddbod_hyst - 21 - mv avdd response time t avddbod_delay supply drops at 0.1v/s rate - 2.4 - s em4 bod threshold v em4dbod avdd rising - - tbd v avdd falling tbd - - v em4 bod hysteresis v em4bod_hyst - 46 - mv em4 response time t em4bod_delay supply drops at 0.1v/s rate - tbd - ns efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 17
4.1.7 oscillators 4.1.7.1 lfxo table 4.9. lfxo parameter symbol test condition min typ max unit crystal frequency f lfxo - 32.768 - khz supported crystal equivalent series resistance (esr) esr lfxo - - 70 k? supported range of crystal load capacitance 1 c lfxo_cl 6 - 18 pf on-chip tuning cap range 2 c lfxo_t on each of lfxtal_n and lfxtal_p pins 8 - 40 pf on-chip tuning cap step size ss lfxo - 0.25 - pf lfxo current consumption on avdd 3 after startup i lfxo_ana esr = 30 k?, c l =12.5 pf, gain 4 = 3, agc 4 = 1 - 273 - na start- up time t lfxo esr=30 k?, c l =12.5 pf, gain 4 =2 - 308 - ms note: 1. total load capacitance as seen by the crystal 2. the effective load capacitance seen by the crystal will be c lfxo_t /2. this is because each xtal pin has a tuning cap and the two caps will be seen in series by the crystal. 3. current consumption on dvdd instead if anasw=1 in emu_pwrctrl register 4. in cmu_lfxoctrl register efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 18
4.1.7.2 hfxo table 4.10. hfxo parameter symbol test condition min typ max unit crystal frequency f hfxo 38 38.4 40 mhz supported crystal equivalent series resistance (esr) esr hfxo crystal frequency 38.4 mhz - - 60 ? supported range of crystal load capacitance 1 c hfxo_cl 6 - 12 pf on-chip tuning cap range 2 c hfxo_t on each of hfxtal_n and hfxtal_p pins 9 20 25 pf on-chip tuning capacitance step ss hfxo - 0.04 - pf startup time t hfxo 38.4 mhz: esr=50 ?, c l = 10 pf, boost 3 = 2 - 300 - s frequency tolerance for the crystal ft hfxo 38.4 mhz, esr = 50 ?, cl = 10 pf -40 - 40 ppm note: 1. total load capacitance as seen by the crystal 2. the effective load capacitance seen by the crystal will be c hfxo_t /2. this is because each xtal pin has a tuning cap and the two caps will be seen in series by the crystal. 3. in cmu_hfxoctrl register 4.1.7.3 lfrco table 4.11. lfrco parameter symbol test condition min typ max unit oscillation frequency f lfrco tbd 32.768 tbd khz startup time t lfrco - 500 - s current consumption on avdd 1 i lfrcoana - tbd - na note: 1. current consumption on dvdd instead if anasw=1 in emu_pwrctrl register efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 19
4.1.7.4 hfrco and auxhfrco table 4.12. hfrco and auxhfrco parameter symbol test condition min typ max unit oscillation frequency f hfrco 38 mhz frequency band tbd 38 tbd mhz 32 mhz frequency band tbd 32 tbd mhz 26 mhz frequency band tbd 26 tbd mhz 19 mhz frequency band tbd 19 tbd mhz 16 mhz frequency band tbd 16 tbd mhz 13 mhz frequency band tbd 13 tbd mhz 7 mhz frequency band tbd 7 tbd mhz 4 mhz frequency band tbd 4 tbd mhz 2 mhz frequency band tbd 2 tbd mhz 1 mhz frequency band tbd 1 tbd mhz start-up time t hfrco f hfrco 19 mhz - 300 - ns 4 < f hfrco < 19 mhz - 1 - s f hfrco 4 mhz - 2.5 - s current consumption on dvdd i hfrcodig f hfrco = 38 mhz - 43 - a f hfrco = 32 mhz - 37 - a f hfrco = 26 mhz - 31 - a f hfrco = 19 mhz - 25 tbd a f hfrco = 16 mhz - 22 - a f hfrco = 13 mhz - 19 - a f hfrco = 7 mhz - 12 - a f hfrco = 4 mhz - 10 - a f hfrco = 2 mhz - 8 - a f hfrco = 1 mhz - 7 - a current consumption on avdd 1 i hfrcoana f hfrco = 38 mhz - 161 - a f hfrco = 32 mhz - 134 - a f hfrco = 26 mhz - 116 - a f hfrco = 19 mhz - 101 tbd a f hfrco = 16 mhz - 88 - a f hfrco = 13 mhz - 81 - a f hfrco = 7 mhz - 69 - a f hfrco = 4 mhz - 23 - a f hfrco = 2 mhz - 23 - a f hfrco = 1 mhz - 23 - a efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 20
parameter symbol test condition min typ max unit step size ss hfrco coarse (% of period) - 0.8 - % fine (% of period) - 0.1 - % period jitter pj hfrco - 0.2 - % rms note: 1. current consumption on dvdd instead if anasw=1 in emu_pwrctrl register 4.1.7.5 ulfrco table 4.13. ulfrco parameter symbol test condition min typ max unit oscillation frequency f ulfrco tbd 1 tbd khz 4.1.8 flash memory characteristics table 4.14. flash memory characteristics 1 parameter symbol test condition min typ max unit flash erase cycles before failure ec flash 10000 - - cycles flash data retention ret flash t amb <85c 10 - - years word (32-bit) programming time t w_prog 20 26 40 s page erase time t perase 20 27 40 ms mass erase time t merase 20 27 40 ms device erase time 2 t derase - 60 tbd ms page erase current 3 i erase - - 3 ma mass or device erase cur- rent 3 - - 5 ma write current 3 i write - - 3 ma note: 1. flash data retention information is published in the quarterly quality and reliability report. 2. device erase is issued over the aap interface and erases all flash, sram, the lock bit (lb) page, and the user data page lock word (ulw) 3. measured at 25c efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 21
4.1.9 gpio table 4.15. gpio parameter symbol test condition min typ max unit input low voltage v ioil - - iovdd*0.3 v input high voltage v ioih iovdd*0.7 - - v output high voltage relative to iovdd v iooh sourcing 3 ma, v dd 3 v, drivestrength 1 = weak iovdd*0.8 - - v sourcing 1.2 ma, v dd 1.62 v, drivestrength 1 = weak iovdd*0.6 - - v sourcing 20 ma, v dd 3 v, drivestrength 1 = strong iovdd*0.8 - - v sourcing 8 ma, v dd 1.62 v, drivestrength 1 = strong iovdd*0.6 - - v output low voltage relative to iovdd v iool sinking 3 ma, v dd 3 v, drivestrength 1 = weak - - iovdd*0.2 v sinking 1.2 ma, v dd 1.62 v, drivestrength 1 = weak - - iovdd*0.4 v sinking 20 ma, v dd 3 v, drivestrength 1 = strong - - iovdd*0.2 v sinking 8 ma, v dd 1.62 v, drivestrength 1 = strong - - iovdd*0.4 v input leakage current i ioleak gpio iovdd - 0.1 tbd na input leakage current on 5vtol pads above iovdd i 5vtolleak iovdd < gpio iovdd + 2 v - 3.3 15 a i/o pin pull-up resistor r pu tbd 43 tbd k? i/o pin pull-down resistor r pd tbd 43 tbd k? pulse width of pulses re- moved by the glitch suppres- sion filter t ioglitch tbd 25 tbd ns output fall time, from 70% to 30% of v io t ioof c l = 50pf, drivestrength 1 = strong, slewrate 1 = 0x6 - tbd - ns c l = 50pf, drivestrength 1 = weak, slewrate 1 = 0x6 - tbd - ns efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 22
parameter symbol test condition min typ max unit output rise time, from 30% to 70% of v io t ioor c l = 50pf, drivestrength 1 = strong, slewrate = 0x6 1 - tbd - ns c l = 50pf, drivestrength 1 = weak, slewrate 1 = 0x6 - tbd - ns note: 1. in gpio_pn_ctrl register 4.1.10 vmon table 4.16. vmon parameter symbol test condition min typ max unit vmon supply current i vmon in em0 or em1, 1 supply moni- tored - 5.8 - a in em0 or em1, 4 supplies moni- tored - 11.8 - a in em2, em3 or em4, 1 supply monitored - 62 - na in em2, em3 or em4, 4 supplies monitored - 99 - na vmon loading of monitored supply i sense in em0 or em1 - 2 - a in em2, em3 or em4 - 2 - na threshold range v vmon_range tbd - tbd v threshold step size n vmon_stesp coarse - 200 - mv fine - 20 - mv response time t vmon_res supply drops at 1v/s rate - 500 - ns hysteresis v vmon_hyst - 26 - mv efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 23
4.1.11 adc table 4.17. adc parameter symbol test condition min typ max unit resolution v resolution 6 - 12 bits input voltage range v adcin single ended 0 - 2*v ref v differential -v ref - v ref v input range of external refer- ence voltage, single ended and differential v adcrefin_p 1 - v avdd v power supply rejection 1 psrr adc at dc - 80 - db analog input common mode rejection ratio cmrr adc at dc - 80 - db current on dvdd, using in- ternal reference buffer. con- tinous operation. warmup- mode 2 = keepadcwarm i adcdig_conti- nous 1 msps / 16 mhz adcclk, biasprog 3 = 0 - 145 - a 250 ksps / 4 mhz adcclk, bia- sprog 3 = 6 - 90 - a 62.5 ksps / 1 mhz adcclk, biasprog 3 = 15 - 85 - a current on avdd 4 , using in- ternal reference buffer. con- tinous operation. warmup- mode 2 = keepadcwarm i adcana_conti- nous 1 msps / 16 mhz adcclk, biasprog 3 = 0 - 286 - a 250 ksps / 4 mhz adcclk, bia- sprog 3 = 6 - 155 - a 62.5 ksps / 1 mhz adcclk, biasprog 3 = 15 - 102 - a current on avdd 4 , using in- ternal reference buffer. duty- cycled operation. warmup- mode 2 = normal i adcana_normal 35 ksps / 16 mhz adcclk, biasprog 3 = 0 - 44 - a 5 ksps / 16 mhz adcclk, biasprog 3 = 0 - 6 - a current on avdd 4 , using in- ternal reference buffer. duty- cycled operation. warmup- mode 2 = keepinstandby or keepinslowacc i adcana_stand- by 125 ksps / 16 mhz adcclk, biasprog 3 = 0 - 117 - a 5 ksps / 16 mhz adcclk, biasprog 3 = 0 - 78 - a adc clock frequency f adcclk - - 16 mhz throughput rate f adcrate - - 1 msps conversion time 5 t adcconv 6 bit - 7 - cycles 10 bit - 11 - cycles 12 bit - 13 - cycles efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 24
parameter symbol test condition min typ max unit startup time of reference generator and adc core in normal mode t adcstart warmupmode 2 = normal - - 5 s from standby mode warmupmode 2 = keepin- standby or keepinslowacc - - 1 s sndr at 1msps and f in = 10khz sndr adc internal reference, 2.5 v full-scale, differential (-1.25, 1.25) tbd 67 - db vrefp_in = 1.25 v direct mode with 2.5 v full-scale, differential - 68 - db spurious-free dynamic range (sfdr) sfdr adc 1 msamples/s, 10 khz full-scale sine wave - 75 - db input referred adc noise, rms v ref_noise including quantization noise and distortion - 380 - v offset error v adcoffseterr tbd 1 tbd lsb gain error in adc v adc_gain using internal reference - -0.2 tbd % using external reference - -1 - % differential non-linearity (dnl) dnl adc 12 bit resolution -1 - tbd lsb integral non-linearity (inl), end point method inl adc 12 bit resolution tbd - tbd lsb temperature sensor slope m tsense - -1.84 - mv/c note: 1. psrr is referenced to avdd when anasw=0 and to dvdd when anasw=1 in emu_pwrctrl 2. in adcn_cntl register 3. in adcn_biasprog register 4. current consumption on dvdd instead if anasw=1 in emu_pwrctrl register 5. derived from adcclk efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 25
4.1.12 idac table 4.18. idac parameter symbol test condition min typ max unit number of ranges n idac_ranges - 4 - - output current i idac_out rangsel 1 = range0 0.05 - 1.6 a rangsel 1 = range1 1.6 - 4.7 a rangsel 1 = range2 0.5 - 16 a rangsel 1 = range3 2 - 64 a linear steps within each range n idac_steps - 32 - step size ss idac rangsel 1 = range0 - 50 - na rangsel 1 = range1 - 100 - na rangsel 1 = range2 - 500 - na rangsel 1 = range3 - 2 - a total accuracy, stepsel 1 = 0x10 acc idac continuous mode, avdd=3.3v, t = 25c tbd - tbd % continuous mode tbd - tbd % em2 or em3 tbd - tbd % start up time t idac_su output within 1% of steady state value - 5 - s settling time, (output settled within 1% of steady state val- ue) t idac_settle range setting is changed - 5 - s step value is changed - 1 - s current consumption in con- tinuous mode 2 i idac source mode, excluding output current - 8.9 - a sink mode, excluding output cur- rent - 12 - a output voltage compliance in source mode, source current change relative to current sourced at 0 v i comp_src rangesel1=0, output voltage = min(v iovdd , v avdd 2 -100 mv) - 0.16 - % rangesel1=1, output voltage = min(v iovdd , v avdd 2 -100 mv) - 0.08 - % rangesel1=2, output voltage = min(v iovdd , v avdd 2 -150 mv) - 0.03 - % rangesel1=3, output voltage = min(v iovdd , v avdd 2 -250 mv) - 0.03 - % efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 26
parameter symbol test condition min typ max unit output voltage compliance in sink mode, sink current change relative to current sunk at iovdd i comp_sink rangesel1=0, output voltage = 100 mv - 0.82 - % rangesel1=1, output voltage = 100 mv - 0.65 - % rangesel1=2, output voltage = 150 mv - 0.4 - % rangesel1=3, output voltage = 250 mv - 0.25 - % note: 1. in idac_curprog register 2. the idac is supplied by either avdd, dvdd, or iovdd based on the setting of anasw in the emu_pwrctrl register and pwrsel in the idac_ctrl register. setting pwrsel to 1 selects iovdd. with pwrsel cleared to 0, anasw selects be- tween avdd (0) and dvdd (1). efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 27
4.1.13 analog comparator (acmp) table 4.19. acmp parameter symbol test condition min typ max unit input voltage range v acmpin cmpvdd = acmpn_ctrl_pwrsel 1 0 - cmpvdd v active current not including voltage reference i acmp biasprog 2 = 1, fullbias 2 = 0 - 50 - na biasprog 2 = 0x10, fullbias 2 = 0 - 306 - na biasprog 2 = 0x20, fullbias 2 = 1 - 74 tbd a current consumption of inter- nal voltage reference, i acmpref vlp selected as input using 2.5v reference / 4 (0.625v) - 50 - na vlp selected as input using vdd - 20 - na vbdiv selected as input using 1.25 v reference / 1 - 3 - a vadiv selected as input using vdd/1 - 2 - a hysteresis v acmphyst hystsel 3 = hyst0 - 0 tbd mv hystsel 3 = hyst1 - 12 - mv hystsel 3 = hyst2 - 22 - mv hystsel 3 = hyst3 - 30 - mv hystsel 3 = hyst4 - 36 - mv hystsel 3 = hyst5 - 41 - mv hystsel 3 = hyst6 - 47 - mv hystsel 3 = hyst7 - 52 - mv comparator delay t acmpdelay biasprog 2 = 1, fullbias 2 = 0 4 - 30 - s biasprog 2 = 0x10, fullbias 2 = 0 4 - 3.7 - s biasprog 2 = 0x20, fullbias 2 = 1 4 - 35 - ns startup time of reference generator t acmpref biasprog 2 =0x07, fullbias 2 = 1 4 - tbd s offset voltage v acmpoffset - - tbd mv reference voltage v acmpref internal 1.25 v reference tbd 1.25 tbd v internal 2.5 v reference tbd 2.5 tbd v efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 28
parameter symbol test condition min typ max unit capacitive sense internal resistance r csres csressel 5 = 0 - inf - k? csressel 5 = 1 - 15 - k? csressel 5 = 2 - 27 - k? csressel 5 = 3 - 39 - k? csressel 5 = 4 - 51 - k? csressel 5 = 5 - 102 - k? csressel 5 = 6 - 164 - k? csressel 5 = 7 - 239 - k? note: 1. cmpvdd is a supply chosen by the setting in acmpn_ctrl_pwrsel and may be iovdd, avdd or dvdd 2. in acmpn_ctrl register 3. in acmpn_hysteresis register 4. 100 mv differential 5. in acmpn_inputsel register the total acmp current is the sum of the contributions from the acmp and its internal voltage reference as given as: i acmptotal = i acmp + i acmpref i acmpref is zero if an external voltage reference is used. efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 29
4.1.14 i2c i2c standard-mode (sm) table 4.20. i2c standard-mode (sm) 1 parameter symbol test condition min typ max unit scl clock frequency 2 f scl 0 - 100 khz scl clock low time t low 4.7 - - s scl clock high time t high 4 - - s sda set-up time t su,dat 250 - - ns sda hold time 3 t hd,dat 100 - 3450 ns repeated start condition set-up time t su,sta 4.7 - - s (repeated) start condition hold time t hd,sta 4 - - s stop condition set-up time t su,sto 4 - - s bus free time between a stop and start condition t buf 4.7 - - s note: 1. for clhr set to 0 in the i2cn_ctrl register 2. for the minimum hfperclk frequency required in standard-mode, refer to the i2c chapter in the reference manual 3. the maximum sda hold time (t hd,dat ) needs to be met only when the device does not stretch the low time of scl (t low ) efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 30
i2c fast-mode (fm) table 4.21. i2c fast-mode (fm) 1 parameter symbol test condition min typ max unit scl clock frequency 2 f scl 0 - 400 khz scl clock low time t low 1.3 - - s scl clock high time t high 0.6 - - s sda set-up time t su,dat 100 - - ns sda hold time 3 t hd,dat 100 - 900 ns repeated start condition set-up time t su,sta 0.6 - - s (repeated) start condition hold time t hd,sta 0.6 - - s stop condition set-up time t su,sto 0.6 - - s bus free time between a stop and start condition t buf 1.3 - - s note: 1. for clhr set to 1 in the i2cn_ctrl register 2. for the minimum hfperclk frequency required in fast-mode, refer to the i2c chapter in the reference manual 3. the maximum sda hold time (t hd,dat ) needs to be met only when the device does not stretch the low time of scl (t low ) i2c fast-mode plus (fm+) table 4.22. i2c fast-mode plus (fm+) 1 parameter symbol test condition min typ max unit scl clock frequency 2 f scl 0 - 1000 khz scl clock low time t low 0.5 - - s scl clock high time t high 0.26 - - s sda set-up time t su,dat 50 - - ns sda hold time t hd,dat 100 - - ns repeated start condition set-up time t su,sta 0.26 - - s (repeated) start condition hold time t hd,sta 0.26 - - s stop condition set-up time t su,sto 0.26 - - s bus free time between a stop and start condition t buf 0.5 - - s note: 1. for clhr set to 0 or 1 in the i2cn_ctrl register 2. for the minimum hfperclk frequency required in fast-mode plus, refer to the i2c chapter in the reference manual efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 31
4.1.15 usart spi spi master timing table 4.23. spi master timing parameter symbol test condition min typ max unit sclk period 1 2 t sclk 2 * t hfperclk - - ns cs to mosi 1 2 t cs_mo 0 - 8 ns sclk to mosi 1 2 t sclk_mo 3 - 20 ns miso setup time 1 2 t su_mi iovdd = 1.98 v 56 - - ns iovdd = 3.0 v 37 - - ns miso hold time 1 2 t h_mi 6 - - ns note: 1. applies for both clkpha = 0 and clkpha = 1 (figure only shows clkpha = 0) 2. measurement done with 8 pf output loading at 10% and 90% of v dd (figure shows 50% of v dd ) cs sclk clkpol = 0 mosi miso t cs_mo t h_mi t su_mi t sckl_mo t sclk sclk clkpol = 1 figure 4.1. spi master timing diagram efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 32
spi slave timing table 4.24. spi slave timing parameter symbol test condition min typ max unit sckl period 1 2 t sclk_sl 2 * t hfperclk - - ns sclk high period 1 2 t sclk_hi 3 * t hfperclk - - ns sclk low period 1 2 t sclk_lo 3 * t hfperclk - - ns cs active to miso 1 2 t cs_act_mi 4 - 50 ns cs disable to miso 1 2 t cs_dis_mi 4 - 50 ns mosi setup time 1 2 t su_mo 4 - - ns mosi hold time 1 2 t h_mo 3 + 2 * t hfperclk - - ns sclk to miso 1 2 t sclk_mi 16 + t hfperclk - 66 + 2 * t hfperclk ns note: 1. applies for both clkpha = 0 and clkpha = 1 (figure only shows clkpha = 0) 2. measurement done with 8 pf output loading at 10% and 90% of v dd (figure shows 50% of v dd ) cs sclk clkpol = 0 mosi miso t cs_act_mi t sclk_hi t sclk t su_mo t h_mo t sclk_mi t cs_dis_mi t sclk_lo sclk clkpol = 1 figure 4.2. spi slave timing diagram efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 33
4.2 typical performance curves default test conditions: ccm mode, ldcdc = 4.7 h, cdcdc = 1.0 f, vdcdc_i = 3.3 v, vdcdc_o = 1.8 v, fdcdc_ln = 8 mhz load step response in ln (ccm) mode (heavy drive) 1ma 100s/div v sw ln (ccm) and lp mode transition (load: 5ma) vdd,v ron,ohm ron vs supply voltage in bypass mode 2 2.5 3 3.5 4 0.5 1 1.5 2 sw _ pfet _ en 0 sw _ pfet _ en 1 load,ma eff,% efficiency vs load current, ln mode 10 0 10 1 10 2 40 50 60 70 80 90 100 heavy drive medium drive light drive 10 -3 10 -2 10 -1 10 0 10 1 40 50 60 70 80 90 100 load,ma eff,% efficiency vs load current, lp mode lp _ cmp _ bias 3 lp _ cmp _ bias 2 lp _ cmp _ bias 1 lp _ cmp _ bias 0 load,ma relative output droop,mv relative output droop vs load current, lp mode 10 -3 10 -2 10 -1 10 0 10 1 -30 -25 -20 -15 -10 -5 0 5 10 lp _ cmp _ bias 3 lp _ cmp _ bias 2 lp _ cmp _ bias 1 lp _ cmp _ bias 0 10s/div i load dvdd 60mv/div offset:1.8v 2v/div offset:1.8v dvdd 50mv/div offset:1.8v 100ma figure 4.3. dc-dc converter typical performance characteristics efm32pg1 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 34
5. typical connection diagrams 5.1 power typical power supply connections for direct supply, without using the internal dc-dc converter, are shown in the following figure. efm32 c avdd_1 c iovdd iovdd vregvss avdd_0 c avdd_0 c dec v dd power plane ground plane decouple avdd_1 dvdd c dvdd figure 5.1. efm32pg1 typical application circuit: direct supply configuration without dc-dc converter typical power supply circuits using the internal dc-dc converter are shown below. the mcu operates from the dc-dc converter supply. power plane ground plane efm32 c avdd_1 c dec decouple vregvss avdd_0 vregvdd iovdd c avdd_0 c iovdd c dvdd v dd dvdd vregsw c vregsw l vregsw avdd_1 figure 5.2. efm32pg1 typical application circuit: configuration with dc-dc converter efm32pg1 data sheet typical connection diagrams silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 35
5.2 other connections other components or connections may be required to meet the system-level requirements. application note an0002: "hardware de- sign considerations" contains detailed information on these connections. application notes can be accessed on the silicon labs web- site ( www.silabs.com/32bit-appnotes ). efm32pg1 data sheet typical connection diagrams silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 36
6. pin definitions 6.1 efm32pg1 qfn48 definition figure 6.1. efm32pg1 qfn48 pinout table 6.1. device pinout qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 0 vss ground efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 37
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 1 pf0 busax [adc0: aport1xch16 acmp0: aport1xch16 acmp1: aport1xch16] busby [adc0: aport2ych16 acmp0: aport2ych16 acmp1: aport2ych16] tim0_cc0 #24 tim0_cc1 #23 tim0_cc2 #22 tim0_cdti0 #21 tim0_cdti1 #20 tim0_cdti2 #19 tim1_cc0 #24 tim1_cc1 #23 tim1_cc2 #22 tim1_cc3 #21 le- tim0_out0 #24 le- tim0_out1 #23 pcnt0_s0in #24 pcnt0_s1in #23 us0_tx #24 us0_rx #23 us0_clk #22 us0_cs #21 us0_cts #20 us0_rts #19 us1_tx #24 us1_rx #23 us1_clk #22 us1_cs #21 us1_cts #20 us1_rts #19 leu0_tx #24 leu0_rx #23 i2c0_sda #24 i2c0_scl #23 prs_ch0 #0 prs_ch1 #7 prs_ch2 #6 prs_ch3 #5 acmp0_o #24 acmp1_o #24 dbg_swclktck #0 boot_tx 2 pf1 busay [adc0: aport1ych17 acmp0: aport1ych17 acmp1: aport1ych17] busbx [adc0: aport2xch17 acmp0: aport2xch17 acmp1: aport2xch17] tim0_cc0 #25 tim0_cc1 #24 tim0_cc2 #23 tim0_cdti0 #22 tim0_cdti1 #21 tim0_cdti2 #20 tim1_cc0 #25 tim1_cc1 #24 tim1_cc2 #23 tim1_cc3 #22 le- tim0_out0 #25 le- tim0_out1 #24 pcnt0_s0in #25 pcnt0_s1in #24 us0_tx #25 us0_rx #24 us0_clk #23 us0_cs #22 us0_cts #21 us0_rts #20 us1_tx #25 us1_rx #24 us1_clk #23 us1_cs #22 us1_cts #21 us1_rts #20 leu0_tx #25 leu0_rx #24 i2c0_sda #25 i2c0_scl #24 prs_ch0 #1 prs_ch1 #0 prs_ch2 #7 prs_ch3 #6 acmp0_o #25 acmp1_o #25 dbg_swdiotms #0 boot_rx 3 pf2 busax [adc0: aport1xch18 acmp0: aport1xch18 acmp1: aport1xch18] busby [adc0: aport2ych18 acmp0: aport2ych18 acmp1: aport2ych18] tim0_cc0 #26 tim0_cc1 #25 tim0_cc2 #24 tim0_cdti0 #23 tim0_cdti1 #22 tim0_cdti2 #21 tim1_cc0 #26 tim1_cc1 #25 tim1_cc2 #24 tim1_cc3 #23 le- tim0_out0 #26 le- tim0_out1 #25 pcnt0_s0in #26 pcnt0_s1in #25 us0_tx #26 us0_rx #25 us0_clk #24 us0_cs #23 us0_cts #22 us0_rts #21 us1_tx #26 us1_rx #25 us1_clk #24 us1_cs #23 us1_cts #22 us1_rts #21 leu0_tx #26 leu0_rx #25 i2c0_sda #26 i2c0_scl #25 cmu_clk0 #6 prs_ch0 #2 prs_ch1 #1 prs_ch2 #0 prs_ch3 #7 acmp0_o #26 acmp1_o #26 dbg_tdo #0 dbg_swo #0 gpio_em4wu0 4 pf3 busay [adc0: aport1ych19 acmp0: aport1ych19 acmp1: aport1ych19] busbx [adc0: aport2xch19 acmp0: aport2xch19 acmp1: aport2xch19] tim0_cc0 #27 tim0_cc1 #26 tim0_cc2 #25 tim0_cdti0 #24 tim0_cdti1 #23 tim0_cdti2 #22 tim1_cc0 #27 tim1_cc1 #26 tim1_cc2 #25 tim1_cc3 #24 le- tim0_out0 #27 le- tim0_out1 #26 pcnt0_s0in #27 pcnt0_s1in #26 us0_tx #27 us0_rx #26 us0_clk #25 us0_cs #24 us0_cts #23 us0_rts #22 us1_tx #27 us1_rx #26 us1_clk #25 us1_cs #24 us1_cts #23 us1_rts #22 leu0_tx #27 leu0_rx #26 i2c0_sda #27 i2c0_scl #26 cmu_clk1 #6 prs_ch0 #3 prs_ch1 #2 prs_ch2 #1 prs_ch3 #0 acmp0_o #27 acmp1_o #27 dbg_tdi #0 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 38
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 5 pf4 busax [adc0: aport1xch20 acmp0: aport1xch20 acmp1: aport1xch20] busby [adc0: aport2ych20 acmp0: aport2ych20 acmp1: aport2ych20] tim0_cc0 #28 tim0_cc1 #27 tim0_cc2 #26 tim0_cdti0 #25 tim0_cdti1 #24 tim0_cdti2 #23 tim1_cc0 #28 tim1_cc1 #27 tim1_cc2 #26 tim1_cc3 #25 le- tim0_out0 #28 le- tim0_out1 #27 pcnt0_s0in #28 pcnt0_s1in #27 us0_tx #28 us0_rx #27 us0_clk #26 us0_cs #25 us0_cts #24 us0_rts #23 us1_tx #28 us1_rx #27 us1_clk #26 us1_cs #25 us1_cts #24 us1_rts #23 leu0_tx #28 leu0_rx #27 i2c0_sda #28 i2c0_scl #27 prs_ch0 #4 prs_ch1 #3 prs_ch2 #2 prs_ch3 #1 acmp0_o #28 acmp1_o #28 6 pf5 busay [adc0: aport1ych21 acmp0: aport1ych21 acmp1: aport1ych21] busbx [adc0: aport2xch21 acmp0: aport2xch21 acmp1: aport2xch21] tim0_cc0 #29 tim0_cc1 #28 tim0_cc2 #27 tim0_cdti0 #26 tim0_cdti1 #25 tim0_cdti2 #24 tim1_cc0 #29 tim1_cc1 #28 tim1_cc2 #27 tim1_cc3 #26 le- tim0_out0 #29 le- tim0_out1 #28 pcnt0_s0in #29 pcnt0_s1in #28 us0_tx #29 us0_rx #28 us0_clk #27 us0_cs #26 us0_cts #25 us0_rts #24 us1_tx #29 us1_rx #28 us1_clk #27 us1_cs #26 us1_cts #25 us1_rts #24 leu0_tx #29 leu0_rx #28 i2c0_sda #29 i2c0_scl #28 prs_ch0 #5 prs_ch1 #4 prs_ch2 #3 prs_ch3 #2 acmp0_o #29 acmp1_o #29 7 pf6 busax [adc0: aport1xch22 acmp0: aport1xch22 acmp1: aport1xch22] busby [adc0: aport2ych22 acmp0: aport2ych22 acmp1: aport2ych22] tim0_cc0 #30 tim0_cc1 #29 tim0_cc2 #28 tim0_cdti0 #27 tim0_cdti1 #26 tim0_cdti2 #25 tim1_cc0 #30 tim1_cc1 #29 tim1_cc2 #28 tim1_cc3 #27 le- tim0_out0 #30 le- tim0_out1 #29 pcnt0_s0in #30 pcnt0_s1in #29 us0_tx #30 us0_rx #29 us0_clk #28 us0_cs #27 us0_cts #26 us0_rts #25 us1_tx #30 us1_rx #29 us1_clk #28 us1_cs #27 us1_cts #26 us1_rts #25 leu0_tx #30 leu0_rx #29 i2c0_sda #30 i2c0_scl #29 cmu_clk1 #7 prs_ch0 #6 prs_ch1 #5 prs_ch2 #4 prs_ch3 #3 acmp0_o #30 acmp1_o #30 8 pf7 busay [adc0: aport1ych23 acmp0: aport1ych23 acmp1: aport1ych23] busbx [adc0: aport2xch23 acmp0: aport2xch23 acmp1: aport2xch23] tim0_cc0 #31 tim0_cc1 #30 tim0_cc2 #29 tim0_cdti0 #28 tim0_cdti1 #27 tim0_cdti2 #26 tim1_cc0 #31 tim1_cc1 #30 tim1_cc2 #29 tim1_cc3 #28 le- tim0_out0 #31 le- tim0_out1 #30 pcnt0_s0in #31 pcnt0_s1in #30 us0_tx #31 us0_rx #30 us0_clk #29 us0_cs #28 us0_cts #27 us0_rts #26 us1_tx #31 us1_rx #30 us1_clk #29 us1_cs #28 us1_cts #27 us1_rts #26 leu0_tx #31 leu0_rx #30 i2c0_sda #31 i2c0_scl #30 cmu_clk0 #7 prs_ch0 #7 prs_ch1 #6 prs_ch2 #5 prs_ch3 #4 acmp0_o #31 acmp1_o #31 gpio_em4wu1 9 avdd_1 analog power supply 1. efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 39
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 10 hfxtal_n high frequency crystal input pin. 11 hfxtal_p high frequency crystal output pin. 12 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 13 nc no connect. 14 nc no connect. 15 nc no connect. 16 nc no connect. 17 nc no connect. 18 pd9 buscy [adc0: aport3ych1 acmp0: aport3ych1 acmp1: aport3ych1 idac0: aport1ych1] busdx [adc0: aport4xch1 acmp0: aport4xch1 acmp1: aport4xch1] tim0_cc0 #17 tim0_cc1 #16 tim0_cc2 #15 tim0_cdti0 #14 tim0_cdti1 #13 tim0_cdti2 #12 tim1_cc0 #17 tim1_cc1 #16 tim1_cc2 #15 tim1_cc3 #14 le- tim0_out0 #17 le- tim0_out1 #16 pcnt0_s0in #17 pcnt0_s1in #16 us0_tx #17 us0_rx #16 us0_clk #15 us0_cs #14 us0_cts #13 us0_rts #12 us1_tx #17 us1_rx #16 us1_clk #15 us1_cs #14 us1_cts #13 us1_rts #12 leu0_tx #17 leu0_rx #16 i2c0_sda #17 i2c0_scl #16 cmu_clk0 #4 prs_ch3 #8 prs_ch4 #0 prs_ch5 #6 prs_ch6 #11 acmp0_o #17 acmp1_o #17 19 pd10 buscx [adc0: aport3xch2 acmp0: aport3xch2 acmp1: aport3xch2 idac0: aport1xch2] busdy [adc0: aport4ych2 acmp0: aport4ych2 acmp1: aport4ych2] tim0_cc0 #18 tim0_cc1 #17 tim0_cc2 #16 tim0_cdti0 #15 tim0_cdti1 #14 tim0_cdti2 #13 tim1_cc0 #18 tim1_cc1 #17 tim1_cc2 #16 tim1_cc3 #15 le- tim0_out0 #18 le- tim0_out1 #17 pcnt0_s0in #18 pcnt0_s1in #17 us0_tx #18 us0_rx #17 us0_clk #16 us0_cs #15 us0_cts #14 us0_rts #13 us1_tx #18 us1_rx #17 us1_clk #16 us1_cs #15 us1_cts #14 us1_rts #13 leu0_tx #18 leu0_rx #17 i2c0_sda #18 i2c0_scl #17 cmu_clk1 #4 prs_ch3 #9 prs_ch4 #1 prs_ch5 #0 prs_ch6 #12 acmp0_o #18 acmp1_o #18 20 pd11 buscy [adc0: aport3ych3 acmp0: aport3ych3 acmp1: aport3ych3 idac0: aport1ych3] busdx [adc0: aport4xch3 acmp0: aport4xch3 acmp1: aport4xch3] tim0_cc0 #19 tim0_cc1 #18 tim0_cc2 #17 tim0_cdti0 #16 tim0_cdti1 #15 tim0_cdti2 #14 tim1_cc0 #19 tim1_cc1 #18 tim1_cc2 #17 tim1_cc3 #16 le- tim0_out0 #19 le- tim0_out1 #18 pcnt0_s0in #19 pcnt0_s1in #18 us0_tx #19 us0_rx #18 us0_clk #17 us0_cs #16 us0_cts #15 us0_rts #14 us1_tx #19 us1_rx #18 us1_clk #17 us1_cs #16 us1_cts #15 us1_rts #14 leu0_tx #19 leu0_rx #18 i2c0_sda #19 i2c0_scl #18 prs_ch3 #10 prs_ch4 #2 prs_ch5 #1 prs_ch6 #13 acmp0_o #19 acmp1_o #19 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 40
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 21 pd12 buscx [adc0: aport3xch4 acmp0: aport3xch4 acmp1: aport3xch4 idac0: aport1xch4] busdy [adc0: aport4ych4 acmp0: aport4ych4 acmp1: aport4ych4] tim0_cc0 #20 tim0_cc1 #19 tim0_cc2 #18 tim0_cdti0 #17 tim0_cdti1 #16 tim0_cdti2 #15 tim1_cc0 #20 tim1_cc1 #19 tim1_cc2 #18 tim1_cc3 #17 le- tim0_out0 #20 le- tim0_out1 #19 pcnt0_s0in #20 pcnt0_s1in #19 us0_tx #20 us0_rx #19 us0_clk #18 us0_cs #17 us0_cts #16 us0_rts #15 us1_tx #20 us1_rx #19 us1_clk #18 us1_cs #17 us1_cts #16 us1_rts #15 leu0_tx #20 leu0_rx #19 i2c0_sda #20 i2c0_scl #19 prs_ch3 #11 prs_ch4 #3 prs_ch5 #2 prs_ch6 #14 acmp0_o #20 acmp1_o #20 22 pd13 buscy [adc0: aport3ych5 acmp0: aport3ych5 acmp1: aport3ych5 idac0: aport1ych5] busdx [adc0: aport4xch5 acmp0: aport4xch5 acmp1: aport4xch5] tim0_cc0 #21 tim0_cc1 #20 tim0_cc2 #19 tim0_cdti0 #18 tim0_cdti1 #17 tim0_cdti2 #16 tim1_cc0 #21 tim1_cc1 #20 tim1_cc2 #19 tim1_cc3 #18 le- tim0_out0 #21 le- tim0_out1 #20 pcnt0_s0in #21 pcnt0_s1in #20 us0_tx #21 us0_rx #20 us0_clk #19 us0_cs #18 us0_cts #17 us0_rts #16 us1_tx #21 us1_rx #20 us1_clk #19 us1_cs #18 us1_cts #17 us1_rts #16 leu0_tx #21 leu0_rx #20 i2c0_sda #21 i2c0_scl #20 prs_ch3 #12 prs_ch4 #4 prs_ch5 #3 prs_ch6 #15 acmp0_o #21 acmp1_o #21 23 pd14 buscx [adc0: aport3xch6 acmp0: aport3xch6 acmp1: aport3xch6 idac0: aport1xch6] busdy [adc0: aport4ych6 acmp0: aport4ych6 acmp1: aport4ych6] tim0_cc0 #22 tim0_cc1 #21 tim0_cc2 #20 tim0_cdti0 #19 tim0_cdti1 #18 tim0_cdti2 #17 tim1_cc0 #22 tim1_cc1 #21 tim1_cc2 #20 tim1_cc3 #19 le- tim0_out0 #22 le- tim0_out1 #21 pcnt0_s0in #22 pcnt0_s1in #21 us0_tx #22 us0_rx #21 us0_clk #20 us0_cs #19 us0_cts #18 us0_rts #17 us1_tx #22 us1_rx #21 us1_clk #20 us1_cs #19 us1_cts #18 us1_rts #17 leu0_tx #22 leu0_rx #21 i2c0_sda #22 i2c0_scl #21 cmu_clk0 #5 prs_ch3 #13 prs_ch4 #5 prs_ch5 #4 prs_ch6 #16 acmp0_o #22 acmp1_o #22 gpio_em4wu4 24 pd15 buscy [adc0: aport3ych7 acmp0: aport3ych7 acmp1: aport3ych7 idac0: aport1ych7] busdx [adc0: aport4xch7 acmp0: aport4xch7 acmp1: aport4xch7] tim0_cc0 #23 tim0_cc1 #22 tim0_cc2 #21 tim0_cdti0 #20 tim0_cdti1 #19 tim0_cdti2 #18 tim1_cc0 #23 tim1_cc1 #22 tim1_cc2 #21 tim1_cc3 #20 le- tim0_out0 #23 le- tim0_out1 #22 pcnt0_s0in #23 pcnt0_s1in #22 us0_tx #23 us0_rx #22 us0_clk #21 us0_cs #20 us0_cts #19 us0_rts #18 us1_tx #23 us1_rx #22 us1_clk #21 us1_cs #20 us1_cts #19 us1_rts #18 leu0_tx #23 leu0_rx #22 i2c0_sda #23 i2c0_scl #22 cmu_clk1 #5 prs_ch3 #14 prs_ch4 #6 prs_ch5 #5 prs_ch6 #17 acmp0_o #23 acmp1_o #23 dbg_swo #2 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 41
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 25 pa0 adc0_extn buscx [adc0: aport3xch8 acmp0: aport3xch8 acmp1: aport3xch8 idac0: aport1xch8] busdy [adc0: aport4ych8 acmp0: aport4ych8 acmp1: aport4ych8] tim0_cc0 #0 tim0_cc1 #31 tim0_cc2 #30 tim0_cdti0 #29 tim0_cdti1 #28 tim0_cdti2 #27 tim1_cc0 #0 tim1_cc1 #31 tim1_cc2 #30 tim1_cc3 #29 le- tim0_out0 #0 le- tim0_out1 #31 pcnt0_s0in #0 pcnt0_s1in #31 us0_tx #0 us0_rx #31 us0_clk #30 us0_cs #29 us0_cts #28 us0_rts #27 us1_tx #0 us1_rx #31 us1_clk #30 us1_cs #29 us1_cts #28 us1_rts #27 leu0_tx #0 leu0_rx #31 i2c0_sda #0 i2c0_scl #31 cmu_clk1 #0 prs_ch6 #0 prs_ch7 #10 prs_ch8 #9 prs_ch9 #8 acmp0_o #0 acmp1_o #0 26 pa1 adc0_extp buscy [adc0: aport3ych9 acmp0: aport3ych9 acmp1: aport3ych9 idac0: aport1ych9] busdx [adc0: aport4xch9 acmp0: aport4xch9 acmp1: aport4xch9] tim0_cc0 #1 tim0_cc1 #0 tim0_cc2 #31 tim0_cdti0 #30 tim0_cdti1 #29 tim0_cdti2 #28 tim1_cc0 #1 tim1_cc1 #0 tim1_cc2 #31 tim1_cc3 #30 le- tim0_out0 #1 le- tim0_out1 #0 pcnt0_s0in #1 pcnt0_s1in #0 us0_tx #1 us0_rx #0 us0_clk #31 us0_cs #30 us0_cts #29 us0_rts #28 us1_tx #1 us1_rx #0 us1_clk #31 us1_cs #30 us1_cts #29 us1_rts #28 leu0_tx #1 leu0_rx #0 i2c0_sda #1 i2c0_scl #0 cmu_clk0 #0 prs_ch6 #1 prs_ch7 #0 prs_ch8 #10 prs_ch9 #9 acmp0_o #1 acmp1_o #1 27 pa2 buscx [adc0: aport3xch10 acmp0: aport3xch10 acmp1: aport3xch10 idac0: aport1xch10] busdy [adc0: aport4ych10 acmp0: aport4ych10 acmp1: aport4ych10] tim0_cc0 #2 tim0_cc1 #1 tim0_cc2 #0 tim0_cdti0 #31 tim0_cdti1 #30 tim0_cdti2 #29 tim1_cc0 #2 tim1_cc1 #1 tim1_cc2 #0 tim1_cc3 #31 le- tim0_out0 #2 le- tim0_out1 #1 pcnt0_s0in #2 pcnt0_s1in #1 us0_tx #2 us0_rx #1 us0_clk #0 us0_cs #31 us0_cts #30 us0_rts #29 us1_tx #2 us1_rx #1 us1_clk #0 us1_cs #31 us1_cts #30 us1_rts #29 leu0_tx #2 leu0_rx #1 i2c0_sda #2 i2c0_scl #1 prs_ch6 #2 prs_ch7 #1 prs_ch8 #0 prs_ch9 #10 acmp0_o #2 acmp1_o #2 28 pa3 buscy [adc0: aport3ych11 acmp0: aport3ych11 acmp1: aport3ych11 idac0: aport1ych11] busdx [adc0: aport4xch11 acmp0: aport4xch11 acmp1: aport4xch11] tim0_cc0 #3 tim0_cc1 #2 tim0_cc2 #1 tim0_cdti0 #0 tim0_cdti1 #31 tim0_cdti2 #30 tim1_cc0 #3 tim1_cc1 #2 tim1_cc2 #1 tim1_cc3 #0 le- tim0_out0 #3 le- tim0_out1 #2 pcnt0_s0in #3 pcnt0_s1in #2 us0_tx #3 us0_rx #2 us0_clk #1 us0_cs #0 us0_cts #31 us0_rts #30 us1_tx #3 us1_rx #2 us1_clk #1 us1_cs #0 us1_cts #31 us1_rts #30 leu0_tx #3 leu0_rx #2 i2c0_sda #3 i2c0_scl #2 prs_ch6 #3 prs_ch7 #2 prs_ch8 #1 prs_ch9 #0 acmp0_o #3 acmp1_o #3 gpio_em4wu8 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 42
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 29 pa4 buscx [adc0: aport3xch12 acmp0: aport3xch12 acmp1: aport3xch12 idac0: aport1xch12] busdy [adc0: aport4ych12 acmp0: aport4ych12 acmp1: aport4ych12] tim0_cc0 #4 tim0_cc1 #3 tim0_cc2 #2 tim0_cdti0 #1 tim0_cdti1 #0 tim0_cdti2 #31 tim1_cc0 #4 tim1_cc1 #3 tim1_cc2 #2 tim1_cc3 #1 le- tim0_out0 #4 le- tim0_out1 #3 pcnt0_s0in #4 pcnt0_s1in #3 us0_tx #4 us0_rx #3 us0_clk #2 us0_cs #1 us0_cts #0 us0_rts #31 us1_tx #4 us1_rx #3 us1_clk #2 us1_cs #1 us1_cts #0 us1_rts #31 leu0_tx #4 leu0_rx #3 i2c0_sda #4 i2c0_scl #3 prs_ch6 #4 prs_ch7 #3 prs_ch8 #2 prs_ch9 #1 acmp0_o #4 acmp1_o #4 30 pa5 buscy [adc0: aport3ych13 acmp0: aport3ych13 acmp1: aport3ych13 idac0: aport1ych13] busdx [adc0: aport4xch13 acmp0: aport4xch13 acmp1: aport4xch13] tim0_cc0 #5 tim0_cc1 #4 tim0_cc2 #3 tim0_cdti0 #2 tim0_cdti1 #1 tim0_cdti2 #0 tim1_cc0 #5 tim1_cc1 #4 tim1_cc2 #3 tim1_cc3 #2 le- tim0_out0 #5 le- tim0_out1 #4 pcnt0_s0in #5 pcnt0_s1in #4 us0_tx #5 us0_rx #4 us0_clk #3 us0_cs #2 us0_cts #1 us0_rts #0 us1_tx #5 us1_rx #4 us1_clk #3 us1_cs #2 us1_cts #1 us1_rts #0 leu0_tx #5 leu0_rx #4 i2c0_sda #5 i2c0_scl #4 prs_ch6 #5 prs_ch7 #4 prs_ch8 #3 prs_ch9 #2 acmp0_o #5 acmp1_o #5 31 pb11 buscy [adc0: aport3ych27 acmp0: aport3ych27 acmp1: aport3ych27 idac0: aport1ych27] busdx [adc0: aport4xch27 acmp0: aport4xch27 acmp1: aport4xch27] tim0_cc0 #6 tim0_cc1 #5 tim0_cc2 #4 tim0_cdti0 #3 tim0_cdti1 #2 tim0_cdti2 #1 tim1_cc0 #6 tim1_cc1 #5 tim1_cc2 #4 tim1_cc3 #3 le- tim0_out0 #6 le- tim0_out1 #5 pcnt0_s0in #6 pcnt0_s1in #5 us0_tx #6 us0_rx #5 us0_clk #4 us0_cs #3 us0_cts #2 us0_rts #1 us1_tx #6 us1_rx #5 us1_clk #4 us1_cs #3 us1_cts #2 us1_rts #1 leu0_tx #6 leu0_rx #5 i2c0_sda #6 i2c0_scl #5 prs_ch6 #6 prs_ch7 #5 prs_ch8 #4 prs_ch9 #3 acmp0_o #6 acmp1_o #6 32 pb12 buscx [adc0: aport3xch28 acmp0: aport3xch28 acmp1: aport3xch28 idac0: aport1xch28] busdy [adc0: aport4ych28 acmp0: aport4ych28 acmp1: aport4ych28] tim0_cc0 #7 tim0_cc1 #6 tim0_cc2 #5 tim0_cdti0 #4 tim0_cdti1 #3 tim0_cdti2 #2 tim1_cc0 #7 tim1_cc1 #6 tim1_cc2 #5 tim1_cc3 #4 le- tim0_out0 #7 le- tim0_out1 #6 pcnt0_s0in #7 pcnt0_s1in #6 us0_tx #7 us0_rx #6 us0_clk #5 us0_cs #4 us0_cts #3 us0_rts #2 us1_tx #7 us1_rx #6 us1_clk #5 us1_cs #4 us1_cts #3 us1_rts #2 leu0_tx #7 leu0_rx #6 i2c0_sda #7 i2c0_scl #6 prs_ch6 #7 prs_ch7 #6 prs_ch8 #5 prs_ch9 #4 acmp0_o #7 acmp1_o #7 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 43
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 33 pb13 buscy [adc0: aport3ych29 acmp0: aport3ych29 acmp1: aport3ych29 idac0: aport1ych29] busdx [adc0: aport4xch29 acmp0: aport4xch29 acmp1: aport4xch29] tim0_cc0 #8 tim0_cc1 #7 tim0_cc2 #6 tim0_cdti0 #5 tim0_cdti1 #4 tim0_cdti2 #3 tim1_cc0 #8 tim1_cc1 #7 tim1_cc2 #6 tim1_cc3 #5 le- tim0_out0 #8 le- tim0_out1 #7 pcnt0_s0in #8 pcnt0_s1in #7 us0_tx #8 us0_rx #7 us0_clk #6 us0_cs #5 us0_cts #4 us0_rts #3 us1_tx #8 us1_rx #7 us1_clk #6 us1_cs #5 us1_cts #4 us1_rts #3 leu0_tx #8 leu0_rx #7 i2c0_sda #8 i2c0_scl #7 prs_ch6 #8 prs_ch7 #7 prs_ch8 #6 prs_ch9 #5 acmp0_o #8 acmp1_o #8 dbg_swo #1 gpio_em4wu9 34 avdd_0 analog power supply 0. 35 pb14 lfxtal_n buscx [adc0: aport3xch30 acmp0: aport3xch30 acmp1: aport3xch30 idac0: aport1xch30] busdy [adc0: aport4ych30 acmp0: aport4ych30 acmp1: aport4ych30] tim0_cc0 #9 tim0_cc1 #8 tim0_cc2 #7 tim0_cdti0 #6 tim0_cdti1 #5 tim0_cdti2 #4 tim1_cc0 #9 tim1_cc1 #8 tim1_cc2 #7 tim1_cc3 #6 le- tim0_out0 #9 le- tim0_out1 #8 pcnt0_s0in #9 pcnt0_s1in #8 us0_tx #9 us0_rx #8 us0_clk #7 us0_cs #6 us0_cts #5 us0_rts #4 us1_tx #9 us1_rx #8 us1_clk #7 us1_cs #6 us1_cts #5 us1_rts #4 leu0_tx #9 leu0_rx #8 i2c0_sda #9 i2c0_scl #8 cmu_clk1 #1 prs_ch6 #9 prs_ch7 #8 prs_ch8 #7 prs_ch9 #6 acmp0_o #9 acmp1_o #9 36 pb15 lfxtal_p buscy [adc0: aport3ych31 acmp0: aport3ych31 acmp1: aport3ych31 idac0: aport1ych31] busdx [adc0: aport4xch31 acmp0: aport4xch31 acmp1: aport4xch31] tim0_cc0 #10 tim0_cc1 #9 tim0_cc2 #8 tim0_cdti0 #7 tim0_cdti1 #6 tim0_cdti2 #5 tim1_cc0 #10 tim1_cc1 #9 tim1_cc2 #8 tim1_cc3 #7 le- tim0_out0 #10 le- tim0_out1 #9 pcnt0_s0in #10 pcnt0_s1in #9 us0_tx #10 us0_rx #9 us0_clk #8 us0_cs #7 us0_cts #6 us0_rts #5 us1_tx #10 us1_rx #9 us1_clk #8 us1_cs #7 us1_cts #6 us1_rts #5 leu0_tx #10 leu0_rx #9 i2c0_sda #10 i2c0_scl #9 cmu_clk0 #1 prs_ch6 #10 prs_ch7 #9 prs_ch8 #8 prs_ch9 #7 acmp0_o #10 acmp1_o #10 37 vregvss voltage regulator vss 38 vregsw dcdc regulator switching node 39 vregvdd voltage regulator vdd input 40 dvdd digital power supply. 41 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 42 iovdd digital io power supply. efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 44
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 43 pc6 busax [adc0: aport1xch6 acmp0: aport1xch6 acmp1: aport1xch6] busby [adc0: aport2ych6 acmp0: aport2ych6 acmp1: aport2ych6] tim0_cc0 #11 tim0_cc1 #10 tim0_cc2 #9 tim0_cdti0 #8 tim0_cdti1 #7 tim0_cdti2 #6 tim1_cc0 #11 tim1_cc1 #10 tim1_cc2 #9 tim1_cc3 #8 le- tim0_out0 #11 le- tim0_out1 #10 pcnt0_s0in #11 pcnt0_s1in #10 us0_tx #11 us0_rx #10 us0_clk #9 us0_cs #8 us0_cts #7 us0_rts #6 us1_tx #11 us1_rx #10 us1_clk #9 us1_cs #8 us1_cts #7 us1_rts #6 leu0_tx #11 leu0_rx #10 i2c0_sda #11 i2c0_scl #10 cmu_clk0 #2 prs_ch0 #8 prs_ch9 #11 prs_ch10 #0 prs_ch11 #5 acmp0_o #11 acmp1_o #11 44 pc7 busay [adc0: aport1ych7 acmp0: aport1ych7 acmp1: aport1ych7] busbx [adc0: aport2xch7 acmp0: aport2xch7 acmp1: aport2xch7] tim0_cc0 #12 tim0_cc1 #11 tim0_cc2 #10 tim0_cdti0 #9 tim0_cdti1 #8 tim0_cdti2 #7 tim1_cc0 #12 tim1_cc1 #11 tim1_cc2 #10 tim1_cc3 #9 le- tim0_out0 #12 le- tim0_out1 #11 pcnt0_s0in #12 pcnt0_s1in #11 us0_tx #12 us0_rx #11 us0_clk #10 us0_cs #9 us0_cts #8 us0_rts #7 us1_tx #12 us1_rx #11 us1_clk #10 us1_cs #9 us1_cts #8 us1_rts #7 leu0_tx #12 leu0_rx #11 i2c0_sda #12 i2c0_scl #11 cmu_clk1 #2 prs_ch0 #9 prs_ch9 #12 prs_ch10 #1 prs_ch11 #0 acmp0_o #12 acmp1_o #12 45 pc8 busax [adc0: aport1xch8 acmp0: aport1xch8 acmp1: aport1xch8] busby [adc0: aport2ych8 acmp0: aport2ych8 acmp1: aport2ych8] tim0_cc0 #13 tim0_cc1 #12 tim0_cc2 #11 tim0_cdti0 #10 tim0_cdti1 #9 tim0_cdti2 #8 tim1_cc0 #13 tim1_cc1 #12 tim1_cc2 #11 tim1_cc3 #10 le- tim0_out0 #13 le- tim0_out1 #12 pcnt0_s0in #13 pcnt0_s1in #12 us0_tx #13 us0_rx #12 us0_clk #11 us0_cs #10 us0_cts #9 us0_rts #8 us1_tx #13 us1_rx #12 us1_clk #11 us1_cs #10 us1_cts #9 us1_rts #8 leu0_tx #13 leu0_rx #12 i2c0_sda #13 i2c0_scl #12 prs_ch0 #10 prs_ch9 #13 prs_ch10 #2 prs_ch11 #1 acmp0_o #13 acmp1_o #13 46 pc9 busay [adc0: aport1ych9 acmp0: aport1ych9 acmp1: aport1ych9] busbx [adc0: aport2xch9 acmp0: aport2xch9 acmp1: aport2xch9] tim0_cc0 #14 tim0_cc1 #13 tim0_cc2 #12 tim0_cdti0 #11 tim0_cdti1 #10 tim0_cdti2 #9 tim1_cc0 #14 tim1_cc1 #13 tim1_cc2 #12 tim1_cc3 #11 le- tim0_out0 #14 le- tim0_out1 #13 pcnt0_s0in #14 pcnt0_s1in #13 us0_tx #14 us0_rx #13 us0_clk #12 us0_cs #11 us0_cts #10 us0_rts #9 us1_tx #14 us1_rx #13 us1_clk #12 us1_cs #11 us1_cts #10 us1_rts #9 leu0_tx #14 leu0_rx #13 i2c0_sda #14 i2c0_scl #13 prs_ch0 #11 prs_ch9 #14 prs_ch10 #3 prs_ch11 #2 acmp0_o #14 acmp1_o #14 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 45
qfn48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 47 pc10 busax [adc0: aport1xch10 acmp0: aport1xch10 acmp1: aport1xch10] busby [adc0: aport2ych10 acmp0: aport2ych10 acmp1: aport2ych10] tim0_cc0 #15 tim0_cc1 #14 tim0_cc2 #13 tim0_cdti0 #12 tim0_cdti1 #11 tim0_cdti2 #10 tim1_cc0 #15 tim1_cc1 #14 tim1_cc2 #13 tim1_cc3 #12 le- tim0_out0 #15 le- tim0_out1 #14 pcnt0_s0in #15 pcnt0_s1in #14 us0_tx #15 us0_rx #14 us0_clk #13 us0_cs #12 us0_cts #11 us0_rts #10 us1_tx #15 us1_rx #14 us1_clk #13 us1_cs #12 us1_cts #11 us1_rts #10 leu0_tx #15 leu0_rx #14 i2c0_sda #15 i2c0_scl #14 cmu_clk1 #3 prs_ch0 #12 prs_ch9 #15 prs_ch10 #4 prs_ch11 #3 acmp0_o #15 acmp1_o #15 gpio_em4wu12 48 pc11 busay [adc0: aport1ych11 acmp0: aport1ych11 acmp1: aport1ych11] busbx [adc0: aport2xch11 acmp0: aport2xch11 acmp1: aport2xch11] tim0_cc0 #16 tim0_cc1 #15 tim0_cc2 #14 tim0_cdti0 #13 tim0_cdti1 #12 tim0_cdti2 #11 tim1_cc0 #16 tim1_cc1 #15 tim1_cc2 #14 tim1_cc3 #13 le- tim0_out0 #16 le- tim0_out1 #15 pcnt0_s0in #16 pcnt0_s1in #15 us0_tx #16 us0_rx #15 us0_clk #14 us0_cs #13 us0_cts #12 us0_rts #11 us1_tx #16 us1_rx #15 us1_clk #14 us1_cs #13 us1_cts #12 us1_rts #11 leu0_tx #16 leu0_rx #15 i2c0_sda #16 i2c0_scl #15 cmu_clk0 #3 prs_ch0 #13 prs_ch9 #16 prs_ch10 #5 prs_ch11 #4 acmp0_o #16 acmp1_o #16 dbg_swo #3 6.1.1 gpio pinout overview the gpio pins are organized as 16-bit ports indicated by letters a through f, and the individual pins on each port is indicated by a number from 15 down to 0. table 6.2. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a - - - - - - - - - - pa5 (5v) pa4 (5v) pa3 (5v) pa2 (5v) pa1 pa0 port b pb15 pb14 pb13 (5v) pb12 (5v) pb11 (5v) - - - - - - - - - - - port c - - - - pc11 (5v) pc10 (5v) pc9 (5v) pc8 (5v) pc7 (5v) pc6 (5v) - - - - - - port d pd15 (5v) pd14 (5v) pd13 (5v) pd12 (5v) pd11 (5v) pd10 (5v) pd9 (5v) - - - - - - - - - port e - - - - - - - - - - - - - - - - port f - - - - - - - - pf7 (5v) pf6 (5v) pf5 (5v) pf4 (5v) pf3 (5v) pf2 (5v) pf1 (5v) pf0 (5v) efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 46
6.2 efm32pg1 qfn32 with dc-dc definition figure 6.2. efm32pg1 qfn32 with dc-dc converter pinout efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 47
table 6.3. device pinout qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 0 vss ground 1 pf0 busax [adc0: aport1xch16 acmp0: aport1xch16 acmp1: aport1xch16] busby [adc0: aport2ych16 acmp0: aport2ych16 acmp1: aport2ych16] tim0_cc0 #24 tim0_cc1 #23 tim0_cc2 #22 tim0_cdti0 #21 tim0_cdti1 #20 tim0_cdti2 #19 tim1_cc0 #24 tim1_cc1 #23 tim1_cc2 #22 tim1_cc3 #21 le- tim0_out0 #24 le- tim0_out1 #23 pcnt0_s0in #24 pcnt0_s1in #23 us0_tx #24 us0_rx #23 us0_clk #22 us0_cs #21 us0_cts #20 us0_rts #19 us1_tx #24 us1_rx #23 us1_clk #22 us1_cs #21 us1_cts #20 us1_rts #19 leu0_tx #24 leu0_rx #23 i2c0_sda #24 i2c0_scl #23 prs_ch0 #0 prs_ch1 #7 prs_ch2 #6 prs_ch3 #5 acmp0_o #24 acmp1_o #24 dbg_swclktck #0 boot_tx 2 pf1 busay [adc0: aport1ych17 acmp0: aport1ych17 acmp1: aport1ych17] busbx [adc0: aport2xch17 acmp0: aport2xch17 acmp1: aport2xch17] tim0_cc0 #25 tim0_cc1 #24 tim0_cc2 #23 tim0_cdti0 #22 tim0_cdti1 #21 tim0_cdti2 #20 tim1_cc0 #25 tim1_cc1 #24 tim1_cc2 #23 tim1_cc3 #22 le- tim0_out0 #25 le- tim0_out1 #24 pcnt0_s0in #25 pcnt0_s1in #24 us0_tx #25 us0_rx #24 us0_clk #23 us0_cs #22 us0_cts #21 us0_rts #20 us1_tx #25 us1_rx #24 us1_clk #23 us1_cs #22 us1_cts #21 us1_rts #20 leu0_tx #25 leu0_rx #24 i2c0_sda #25 i2c0_scl #24 prs_ch0 #1 prs_ch1 #0 prs_ch2 #7 prs_ch3 #6 acmp0_o #25 acmp1_o #25 dbg_swdiotms #0 boot_rx 3 pf2 busax [adc0: aport1xch18 acmp0: aport1xch18 acmp1: aport1xch18] busby [adc0: aport2ych18 acmp0: aport2ych18 acmp1: aport2ych18] tim0_cc0 #26 tim0_cc1 #25 tim0_cc2 #24 tim0_cdti0 #23 tim0_cdti1 #22 tim0_cdti2 #21 tim1_cc0 #26 tim1_cc1 #25 tim1_cc2 #24 tim1_cc3 #23 le- tim0_out0 #26 le- tim0_out1 #25 pcnt0_s0in #26 pcnt0_s1in #25 us0_tx #26 us0_rx #25 us0_clk #24 us0_cs #23 us0_cts #22 us0_rts #21 us1_tx #26 us1_rx #25 us1_clk #24 us1_cs #23 us1_cts #22 us1_rts #21 leu0_tx #26 leu0_rx #25 i2c0_sda #26 i2c0_scl #25 cmu_clk0 #6 prs_ch0 #2 prs_ch1 #1 prs_ch2 #0 prs_ch3 #7 acmp0_o #26 acmp1_o #26 dbg_tdo #0 dbg_swo #0 gpio_em4wu0 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 48
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 4 pf3 busay [adc0: aport1ych19 acmp0: aport1ych19 acmp1: aport1ych19] busbx [adc0: aport2xch19 acmp0: aport2xch19 acmp1: aport2xch19] tim0_cc0 #27 tim0_cc1 #26 tim0_cc2 #25 tim0_cdti0 #24 tim0_cdti1 #23 tim0_cdti2 #22 tim1_cc0 #27 tim1_cc1 #26 tim1_cc2 #25 tim1_cc3 #24 le- tim0_out0 #27 le- tim0_out1 #26 pcnt0_s0in #27 pcnt0_s1in #26 us0_tx #27 us0_rx #26 us0_clk #25 us0_cs #24 us0_cts #23 us0_rts #22 us1_tx #27 us1_rx #26 us1_clk #25 us1_cs #24 us1_cts #23 us1_rts #22 leu0_tx #27 leu0_rx #26 i2c0_sda #27 i2c0_scl #26 cmu_clk1 #6 prs_ch0 #3 prs_ch1 #2 prs_ch2 #1 prs_ch3 #0 acmp0_o #27 acmp1_o #27 dbg_tdi #0 5 avdd_1 analog power supply 1. 6 hfxtal_n high frequency crystal input pin. 7 hfxtal_p high frequency crystal output pin. 8 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 9 nc no connect. 10 pd9 buscy [adc0: aport3ych1 acmp0: aport3ych1 acmp1: aport3ych1 idac0: aport1ych1] busdx [adc0: aport4xch1 acmp0: aport4xch1 acmp1: aport4xch1] tim0_cc0 #17 tim0_cc1 #16 tim0_cc2 #15 tim0_cdti0 #14 tim0_cdti1 #13 tim0_cdti2 #12 tim1_cc0 #17 tim1_cc1 #16 tim1_cc2 #15 tim1_cc3 #14 le- tim0_out0 #17 le- tim0_out1 #16 pcnt0_s0in #17 pcnt0_s1in #16 us0_tx #17 us0_rx #16 us0_clk #15 us0_cs #14 us0_cts #13 us0_rts #12 us1_tx #17 us1_rx #16 us1_clk #15 us1_cs #14 us1_cts #13 us1_rts #12 leu0_tx #17 leu0_rx #16 i2c0_sda #17 i2c0_scl #16 cmu_clk0 #4 prs_ch3 #8 prs_ch4 #0 prs_ch5 #6 prs_ch6 #11 acmp0_o #17 acmp1_o #17 11 pd10 buscx [adc0: aport3xch2 acmp0: aport3xch2 acmp1: aport3xch2 idac0: aport1xch2] busdy [adc0: aport4ych2 acmp0: aport4ych2 acmp1: aport4ych2] tim0_cc0 #18 tim0_cc1 #17 tim0_cc2 #16 tim0_cdti0 #15 tim0_cdti1 #14 tim0_cdti2 #13 tim1_cc0 #18 tim1_cc1 #17 tim1_cc2 #16 tim1_cc3 #15 le- tim0_out0 #18 le- tim0_out1 #17 pcnt0_s0in #18 pcnt0_s1in #17 us0_tx #18 us0_rx #17 us0_clk #16 us0_cs #15 us0_cts #14 us0_rts #13 us1_tx #18 us1_rx #17 us1_clk #16 us1_cs #15 us1_cts #14 us1_rts #13 leu0_tx #18 leu0_rx #17 i2c0_sda #18 i2c0_scl #17 cmu_clk1 #4 prs_ch3 #9 prs_ch4 #1 prs_ch5 #0 prs_ch6 #12 acmp0_o #18 acmp1_o #18 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 49
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 12 pd11 buscy [adc0: aport3ych3 acmp0: aport3ych3 acmp1: aport3ych3 idac0: aport1ych3] busdx [adc0: aport4xch3 acmp0: aport4xch3 acmp1: aport4xch3] tim0_cc0 #19 tim0_cc1 #18 tim0_cc2 #17 tim0_cdti0 #16 tim0_cdti1 #15 tim0_cdti2 #14 tim1_cc0 #19 tim1_cc1 #18 tim1_cc2 #17 tim1_cc3 #16 le- tim0_out0 #19 le- tim0_out1 #18 pcnt0_s0in #19 pcnt0_s1in #18 us0_tx #19 us0_rx #18 us0_clk #17 us0_cs #16 us0_cts #15 us0_rts #14 us1_tx #19 us1_rx #18 us1_clk #17 us1_cs #16 us1_cts #15 us1_rts #14 leu0_tx #19 leu0_rx #18 i2c0_sda #19 i2c0_scl #18 prs_ch3 #10 prs_ch4 #2 prs_ch5 #1 prs_ch6 #13 acmp0_o #19 acmp1_o #19 13 pd12 buscx [adc0: aport3xch4 acmp0: aport3xch4 acmp1: aport3xch4 idac0: aport1xch4] busdy [adc0: aport4ych4 acmp0: aport4ych4 acmp1: aport4ych4] tim0_cc0 #20 tim0_cc1 #19 tim0_cc2 #18 tim0_cdti0 #17 tim0_cdti1 #16 tim0_cdti2 #15 tim1_cc0 #20 tim1_cc1 #19 tim1_cc2 #18 tim1_cc3 #17 le- tim0_out0 #20 le- tim0_out1 #19 pcnt0_s0in #20 pcnt0_s1in #19 us0_tx #20 us0_rx #19 us0_clk #18 us0_cs #17 us0_cts #16 us0_rts #15 us1_tx #20 us1_rx #19 us1_clk #18 us1_cs #17 us1_cts #16 us1_rts #15 leu0_tx #20 leu0_rx #19 i2c0_sda #20 i2c0_scl #19 prs_ch3 #11 prs_ch4 #3 prs_ch5 #2 prs_ch6 #14 acmp0_o #20 acmp1_o #20 14 pd13 buscy [adc0: aport3ych5 acmp0: aport3ych5 acmp1: aport3ych5 idac0: aport1ych5] busdx [adc0: aport4xch5 acmp0: aport4xch5 acmp1: aport4xch5] tim0_cc0 #21 tim0_cc1 #20 tim0_cc2 #19 tim0_cdti0 #18 tim0_cdti1 #17 tim0_cdti2 #16 tim1_cc0 #21 tim1_cc1 #20 tim1_cc2 #19 tim1_cc3 #18 le- tim0_out0 #21 le- tim0_out1 #20 pcnt0_s0in #21 pcnt0_s1in #20 us0_tx #21 us0_rx #20 us0_clk #19 us0_cs #18 us0_cts #17 us0_rts #16 us1_tx #21 us1_rx #20 us1_clk #19 us1_cs #18 us1_cts #17 us1_rts #16 leu0_tx #21 leu0_rx #20 i2c0_sda #21 i2c0_scl #20 prs_ch3 #12 prs_ch4 #4 prs_ch5 #3 prs_ch6 #15 acmp0_o #21 acmp1_o #21 15 pd14 buscx [adc0: aport3xch6 acmp0: aport3xch6 acmp1: aport3xch6 idac0: aport1xch6] busdy [adc0: aport4ych6 acmp0: aport4ych6 acmp1: aport4ych6] tim0_cc0 #22 tim0_cc1 #21 tim0_cc2 #20 tim0_cdti0 #19 tim0_cdti1 #18 tim0_cdti2 #17 tim1_cc0 #22 tim1_cc1 #21 tim1_cc2 #20 tim1_cc3 #19 le- tim0_out0 #22 le- tim0_out1 #21 pcnt0_s0in #22 pcnt0_s1in #21 us0_tx #22 us0_rx #21 us0_clk #20 us0_cs #19 us0_cts #18 us0_rts #17 us1_tx #22 us1_rx #21 us1_clk #20 us1_cs #19 us1_cts #18 us1_rts #17 leu0_tx #22 leu0_rx #21 i2c0_sda #22 i2c0_scl #21 cmu_clk0 #5 prs_ch3 #13 prs_ch4 #5 prs_ch5 #4 prs_ch6 #16 acmp0_o #22 acmp1_o #22 gpio_em4wu4 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 50
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 16 pd15 buscy [adc0: aport3ych7 acmp0: aport3ych7 acmp1: aport3ych7 idac0: aport1ych7] busdx [adc0: aport4xch7 acmp0: aport4xch7 acmp1: aport4xch7] tim0_cc0 #23 tim0_cc1 #22 tim0_cc2 #21 tim0_cdti0 #20 tim0_cdti1 #19 tim0_cdti2 #18 tim1_cc0 #23 tim1_cc1 #22 tim1_cc2 #21 tim1_cc3 #20 le- tim0_out0 #23 le- tim0_out1 #22 pcnt0_s0in #23 pcnt0_s1in #22 us0_tx #23 us0_rx #22 us0_clk #21 us0_cs #20 us0_cts #19 us0_rts #18 us1_tx #23 us1_rx #22 us1_clk #21 us1_cs #20 us1_cts #19 us1_rts #18 leu0_tx #23 leu0_rx #22 i2c0_sda #23 i2c0_scl #22 cmu_clk1 #5 prs_ch3 #14 prs_ch4 #6 prs_ch5 #5 prs_ch6 #17 acmp0_o #23 acmp1_o #23 dbg_swo #2 17 pa0 adc0_extn buscx [adc0: aport3xch8 acmp0: aport3xch8 acmp1: aport3xch8 idac0: aport1xch8] busdy [adc0: aport4ych8 acmp0: aport4ych8 acmp1: aport4ych8] tim0_cc0 #0 tim0_cc1 #31 tim0_cc2 #30 tim0_cdti0 #29 tim0_cdti1 #28 tim0_cdti2 #27 tim1_cc0 #0 tim1_cc1 #31 tim1_cc2 #30 tim1_cc3 #29 le- tim0_out0 #0 le- tim0_out1 #31 pcnt0_s0in #0 pcnt0_s1in #31 us0_tx #0 us0_rx #31 us0_clk #30 us0_cs #29 us0_cts #28 us0_rts #27 us1_tx #0 us1_rx #31 us1_clk #30 us1_cs #29 us1_cts #28 us1_rts #27 leu0_tx #0 leu0_rx #31 i2c0_sda #0 i2c0_scl #31 cmu_clk1 #0 prs_ch6 #0 prs_ch7 #10 prs_ch8 #9 prs_ch9 #8 acmp0_o #0 acmp1_o #0 18 pa1 adc0_extp buscy [adc0: aport3ych9 acmp0: aport3ych9 acmp1: aport3ych9 idac0: aport1ych9] busdx [adc0: aport4xch9 acmp0: aport4xch9 acmp1: aport4xch9] tim0_cc0 #1 tim0_cc1 #0 tim0_cc2 #31 tim0_cdti0 #30 tim0_cdti1 #29 tim0_cdti2 #28 tim1_cc0 #1 tim1_cc1 #0 tim1_cc2 #31 tim1_cc3 #30 le- tim0_out0 #1 le- tim0_out1 #0 pcnt0_s0in #1 pcnt0_s1in #0 us0_tx #1 us0_rx #0 us0_clk #31 us0_cs #30 us0_cts #29 us0_rts #28 us1_tx #1 us1_rx #0 us1_clk #31 us1_cs #30 us1_cts #29 us1_rts #28 leu0_tx #1 leu0_rx #0 i2c0_sda #1 i2c0_scl #0 cmu_clk0 #0 prs_ch6 #1 prs_ch7 #0 prs_ch8 #10 prs_ch9 #9 acmp0_o #1 acmp1_o #1 19 pb11 buscy [adc0: aport3ych27 acmp0: aport3ych27 acmp1: aport3ych27 idac0: aport1ych27] busdx [adc0: aport4xch27 acmp0: aport4xch27 acmp1: aport4xch27] tim0_cc0 #6 tim0_cc1 #5 tim0_cc2 #4 tim0_cdti0 #3 tim0_cdti1 #2 tim0_cdti2 #1 tim1_cc0 #6 tim1_cc1 #5 tim1_cc2 #4 tim1_cc3 #3 le- tim0_out0 #6 le- tim0_out1 #5 pcnt0_s0in #6 pcnt0_s1in #5 us0_tx #6 us0_rx #5 us0_clk #4 us0_cs #3 us0_cts #2 us0_rts #1 us1_tx #6 us1_rx #5 us1_clk #4 us1_cs #3 us1_cts #2 us1_rts #1 leu0_tx #6 leu0_rx #5 i2c0_sda #6 i2c0_scl #5 prs_ch6 #6 prs_ch7 #5 prs_ch8 #4 prs_ch9 #3 acmp0_o #6 acmp1_o #6 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 51
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 20 pb12 buscx [adc0: aport3xch28 acmp0: aport3xch28 acmp1: aport3xch28 idac0: aport1xch28] busdy [adc0: aport4ych28 acmp0: aport4ych28 acmp1: aport4ych28] tim0_cc0 #7 tim0_cc1 #6 tim0_cc2 #5 tim0_cdti0 #4 tim0_cdti1 #3 tim0_cdti2 #2 tim1_cc0 #7 tim1_cc1 #6 tim1_cc2 #5 tim1_cc3 #4 le- tim0_out0 #7 le- tim0_out1 #6 pcnt0_s0in #7 pcnt0_s1in #6 us0_tx #7 us0_rx #6 us0_clk #5 us0_cs #4 us0_cts #3 us0_rts #2 us1_tx #7 us1_rx #6 us1_clk #5 us1_cs #4 us1_cts #3 us1_rts #2 leu0_tx #7 leu0_rx #6 i2c0_sda #7 i2c0_scl #6 prs_ch6 #7 prs_ch7 #6 prs_ch8 #5 prs_ch9 #4 acmp0_o #7 acmp1_o #7 21 pb13 buscy [adc0: aport3ych29 acmp0: aport3ych29 acmp1: aport3ych29 idac0: aport1ych29] busdx [adc0: aport4xch29 acmp0: aport4xch29 acmp1: aport4xch29] tim0_cc0 #8 tim0_cc1 #7 tim0_cc2 #6 tim0_cdti0 #5 tim0_cdti1 #4 tim0_cdti2 #3 tim1_cc0 #8 tim1_cc1 #7 tim1_cc2 #6 tim1_cc3 #5 le- tim0_out0 #8 le- tim0_out1 #7 pcnt0_s0in #8 pcnt0_s1in #7 us0_tx #8 us0_rx #7 us0_clk #6 us0_cs #5 us0_cts #4 us0_rts #3 us1_tx #8 us1_rx #7 us1_clk #6 us1_cs #5 us1_cts #4 us1_rts #3 leu0_tx #8 leu0_rx #7 i2c0_sda #8 i2c0_scl #7 prs_ch6 #8 prs_ch7 #7 prs_ch8 #6 prs_ch9 #5 acmp0_o #8 acmp1_o #8 dbg_swo #1 gpio_em4wu9 22 avdd_0 analog power supply 0. 23 pb14 lfxtal_n buscx [adc0: aport3xch30 acmp0: aport3xch30 acmp1: aport3xch30 idac0: aport1xch30] busdy [adc0: aport4ych30 acmp0: aport4ych30 acmp1: aport4ych30] tim0_cc0 #9 tim0_cc1 #8 tim0_cc2 #7 tim0_cdti0 #6 tim0_cdti1 #5 tim0_cdti2 #4 tim1_cc0 #9 tim1_cc1 #8 tim1_cc2 #7 tim1_cc3 #6 le- tim0_out0 #9 le- tim0_out1 #8 pcnt0_s0in #9 pcnt0_s1in #8 us0_tx #9 us0_rx #8 us0_clk #7 us0_cs #6 us0_cts #5 us0_rts #4 us1_tx #9 us1_rx #8 us1_clk #7 us1_cs #6 us1_cts #5 us1_rts #4 leu0_tx #9 leu0_rx #8 i2c0_sda #9 i2c0_scl #8 cmu_clk1 #1 prs_ch6 #9 prs_ch7 #8 prs_ch8 #7 prs_ch9 #6 acmp0_o #9 acmp1_o #9 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 52
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 24 pb15 lfxtal_p buscy [adc0: aport3ych31 acmp0: aport3ych31 acmp1: aport3ych31 idac0: aport1ych31] busdx [adc0: aport4xch31 acmp0: aport4xch31 acmp1: aport4xch31] tim0_cc0 #10 tim0_cc1 #9 tim0_cc2 #8 tim0_cdti0 #7 tim0_cdti1 #6 tim0_cdti2 #5 tim1_cc0 #10 tim1_cc1 #9 tim1_cc2 #8 tim1_cc3 #7 le- tim0_out0 #10 le- tim0_out1 #9 pcnt0_s0in #10 pcnt0_s1in #9 us0_tx #10 us0_rx #9 us0_clk #8 us0_cs #7 us0_cts #6 us0_rts #5 us1_tx #10 us1_rx #9 us1_clk #8 us1_cs #7 us1_cts #6 us1_rts #5 leu0_tx #10 leu0_rx #9 i2c0_sda #10 i2c0_scl #9 cmu_clk0 #1 prs_ch6 #10 prs_ch7 #9 prs_ch8 #8 prs_ch9 #7 acmp0_o #10 acmp1_o #10 25 vregvss voltage regulator vss 26 vregsw dcdc regulator switching node 27 vregvdd voltage regulator vdd input 28 dvdd digital power supply. 29 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 30 iovdd digital io power supply. 31 pc10 busax [adc0: aport1xch10 acmp0: aport1xch10 acmp1: aport1xch10] busby [adc0: aport2ych10 acmp0: aport2ych10 acmp1: aport2ych10] tim0_cc0 #15 tim0_cc1 #14 tim0_cc2 #13 tim0_cdti0 #12 tim0_cdti1 #11 tim0_cdti2 #10 tim1_cc0 #15 tim1_cc1 #14 tim1_cc2 #13 tim1_cc3 #12 le- tim0_out0 #15 le- tim0_out1 #14 pcnt0_s0in #15 pcnt0_s1in #14 us0_tx #15 us0_rx #14 us0_clk #13 us0_cs #12 us0_cts #11 us0_rts #10 us1_tx #15 us1_rx #14 us1_clk #13 us1_cs #12 us1_cts #11 us1_rts #10 leu0_tx #15 leu0_rx #14 i2c0_sda #15 i2c0_scl #14 cmu_clk1 #3 prs_ch0 #12 prs_ch9 #15 prs_ch10 #4 prs_ch11 #3 acmp0_o #15 acmp1_o #15 gpio_em4wu12 32 pc11 busay [adc0: aport1ych11 acmp0: aport1ych11 acmp1: aport1ych11] busbx [adc0: aport2xch11 acmp0: aport2xch11 acmp1: aport2xch11] tim0_cc0 #16 tim0_cc1 #15 tim0_cc2 #14 tim0_cdti0 #13 tim0_cdti1 #12 tim0_cdti2 #11 tim1_cc0 #16 tim1_cc1 #15 tim1_cc2 #14 tim1_cc3 #13 le- tim0_out0 #16 le- tim0_out1 #15 pcnt0_s0in #16 pcnt0_s1in #15 us0_tx #16 us0_rx #15 us0_clk #14 us0_cs #13 us0_cts #12 us0_rts #11 us1_tx #16 us1_rx #15 us1_clk #14 us1_cs #13 us1_cts #12 us1_rts #11 leu0_tx #16 leu0_rx #15 i2c0_sda #16 i2c0_scl #15 cmu_clk0 #3 prs_ch0 #13 prs_ch9 #16 prs_ch10 #5 prs_ch11 #4 acmp0_o #16 acmp1_o #16 dbg_swo #3 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 53
6.2.1 gpio pinout overview the gpio pins are organized as 16-bit ports indicated by letters a through f, and the individual pins on each port is indicated by a number from 15 down to 0. table 6.4. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a - - - - - - - - - - - - - - pa1 pa0 port b pb15 pb14 pb13 (5v) pb12 (5v) pb11 (5v) - - - - - - - - - - - port c - - - - pc11 (5v) pc10 (5v) - - - - - - - - - - port d pd15 (5v) pd14 (5v) pd13 (5v) pd12 (5v) pd11 (5v) pd10 (5v) pd9 (5v) - - - - - - - - - port e - - - - - - - - - - - - - - - - port f - - - - - - - - - - - - pf3 (5v) pf2 (5v) pf1 (5v) pf0 (5v) efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 54
6.3 efm32pg1 qfn32 without dc-dc definition figure 6.3. efm32pg1 qfn32 without dc-dc converter pinout efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 55
table 6.5. device pinout qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 0 vregvss voltage regulator vss 1 pf0 busax [adc0: aport1xch16 acmp0: aport1xch16 acmp1: aport1xch16] busby [adc0: aport2ych16 acmp0: aport2ych16 acmp1: aport2ych16] tim0_cc0 #24 tim0_cc1 #23 tim0_cc2 #22 tim0_cdti0 #21 tim0_cdti1 #20 tim0_cdti2 #19 tim1_cc0 #24 tim1_cc1 #23 tim1_cc2 #22 tim1_cc3 #21 le- tim0_out0 #24 le- tim0_out1 #23 pcnt0_s0in #24 pcnt0_s1in #23 us0_tx #24 us0_rx #23 us0_clk #22 us0_cs #21 us0_cts #20 us0_rts #19 us1_tx #24 us1_rx #23 us1_clk #22 us1_cs #21 us1_cts #20 us1_rts #19 leu0_tx #24 leu0_rx #23 i2c0_sda #24 i2c0_scl #23 prs_ch0 #0 prs_ch1 #7 prs_ch2 #6 prs_ch3 #5 acmp0_o #24 acmp1_o #24 dbg_swclktck #0 boot_tx 2 pf1 busay [adc0: aport1ych17 acmp0: aport1ych17 acmp1: aport1ych17] busbx [adc0: aport2xch17 acmp0: aport2xch17 acmp1: aport2xch17] tim0_cc0 #25 tim0_cc1 #24 tim0_cc2 #23 tim0_cdti0 #22 tim0_cdti1 #21 tim0_cdti2 #20 tim1_cc0 #25 tim1_cc1 #24 tim1_cc2 #23 tim1_cc3 #22 le- tim0_out0 #25 le- tim0_out1 #24 pcnt0_s0in #25 pcnt0_s1in #24 us0_tx #25 us0_rx #24 us0_clk #23 us0_cs #22 us0_cts #21 us0_rts #20 us1_tx #25 us1_rx #24 us1_clk #23 us1_cs #22 us1_cts #21 us1_rts #20 leu0_tx #25 leu0_rx #24 i2c0_sda #25 i2c0_scl #24 prs_ch0 #1 prs_ch1 #0 prs_ch2 #7 prs_ch3 #6 acmp0_o #25 acmp1_o #25 dbg_swdiotms #0 boot_rx 3 pf2 busax [adc0: aport1xch18 acmp0: aport1xch18 acmp1: aport1xch18] busby [adc0: aport2ych18 acmp0: aport2ych18 acmp1: aport2ych18] tim0_cc0 #26 tim0_cc1 #25 tim0_cc2 #24 tim0_cdti0 #23 tim0_cdti1 #22 tim0_cdti2 #21 tim1_cc0 #26 tim1_cc1 #25 tim1_cc2 #24 tim1_cc3 #23 le- tim0_out0 #26 le- tim0_out1 #25 pcnt0_s0in #26 pcnt0_s1in #25 us0_tx #26 us0_rx #25 us0_clk #24 us0_cs #23 us0_cts #22 us0_rts #21 us1_tx #26 us1_rx #25 us1_clk #24 us1_cs #23 us1_cts #22 us1_rts #21 leu0_tx #26 leu0_rx #25 i2c0_sda #26 i2c0_scl #25 cmu_clk0 #6 prs_ch0 #2 prs_ch1 #1 prs_ch2 #0 prs_ch3 #7 acmp0_o #26 acmp1_o #26 dbg_tdo #0 dbg_swo #0 gpio_em4wu0 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 56
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 4 pf3 busay [adc0: aport1ych19 acmp0: aport1ych19 acmp1: aport1ych19] busbx [adc0: aport2xch19 acmp0: aport2xch19 acmp1: aport2xch19] tim0_cc0 #27 tim0_cc1 #26 tim0_cc2 #25 tim0_cdti0 #24 tim0_cdti1 #23 tim0_cdti2 #22 tim1_cc0 #27 tim1_cc1 #26 tim1_cc2 #25 tim1_cc3 #24 le- tim0_out0 #27 le- tim0_out1 #26 pcnt0_s0in #27 pcnt0_s1in #26 us0_tx #27 us0_rx #26 us0_clk #25 us0_cs #24 us0_cts #23 us0_rts #22 us1_tx #27 us1_rx #26 us1_clk #25 us1_cs #24 us1_cts #23 us1_rts #22 leu0_tx #27 leu0_rx #26 i2c0_sda #27 i2c0_scl #26 cmu_clk1 #6 prs_ch0 #3 prs_ch1 #2 prs_ch2 #1 prs_ch3 #0 acmp0_o #27 acmp1_o #27 dbg_tdi #0 5 pf4 busax [adc0: aport1xch20 acmp0: aport1xch20 acmp1: aport1xch20] busby [adc0: aport2ych20 acmp0: aport2ych20 acmp1: aport2ych20] tim0_cc0 #28 tim0_cc1 #27 tim0_cc2 #26 tim0_cdti0 #25 tim0_cdti1 #24 tim0_cdti2 #23 tim1_cc0 #28 tim1_cc1 #27 tim1_cc2 #26 tim1_cc3 #25 le- tim0_out0 #28 le- tim0_out1 #27 pcnt0_s0in #28 pcnt0_s1in #27 us0_tx #28 us0_rx #27 us0_clk #26 us0_cs #25 us0_cts #24 us0_rts #23 us1_tx #28 us1_rx #27 us1_clk #26 us1_cs #25 us1_cts #24 us1_rts #23 leu0_tx #28 leu0_rx #27 i2c0_sda #28 i2c0_scl #27 prs_ch0 #4 prs_ch1 #3 prs_ch2 #2 prs_ch3 #1 acmp0_o #28 acmp1_o #28 6 avdd_1 analog power supply 1. 7 hfxtal_n high frequency crystal input pin. 8 hfxtal_p high frequency crystal output pin. 9 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 10 pd9 buscy [adc0: aport3ych1 acmp0: aport3ych1 acmp1: aport3ych1 idac0: aport1ych1] busdx [adc0: aport4xch1 acmp0: aport4xch1 acmp1: aport4xch1] tim0_cc0 #17 tim0_cc1 #16 tim0_cc2 #15 tim0_cdti0 #14 tim0_cdti1 #13 tim0_cdti2 #12 tim1_cc0 #17 tim1_cc1 #16 tim1_cc2 #15 tim1_cc3 #14 le- tim0_out0 #17 le- tim0_out1 #16 pcnt0_s0in #17 pcnt0_s1in #16 us0_tx #17 us0_rx #16 us0_clk #15 us0_cs #14 us0_cts #13 us0_rts #12 us1_tx #17 us1_rx #16 us1_clk #15 us1_cs #14 us1_cts #13 us1_rts #12 leu0_tx #17 leu0_rx #16 i2c0_sda #17 i2c0_scl #16 cmu_clk0 #4 prs_ch3 #8 prs_ch4 #0 prs_ch5 #6 prs_ch6 #11 acmp0_o #17 acmp1_o #17 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 57
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 11 pd10 buscx [adc0: aport3xch2 acmp0: aport3xch2 acmp1: aport3xch2 idac0: aport1xch2] busdy [adc0: aport4ych2 acmp0: aport4ych2 acmp1: aport4ych2] tim0_cc0 #18 tim0_cc1 #17 tim0_cc2 #16 tim0_cdti0 #15 tim0_cdti1 #14 tim0_cdti2 #13 tim1_cc0 #18 tim1_cc1 #17 tim1_cc2 #16 tim1_cc3 #15 le- tim0_out0 #18 le- tim0_out1 #17 pcnt0_s0in #18 pcnt0_s1in #17 us0_tx #18 us0_rx #17 us0_clk #16 us0_cs #15 us0_cts #14 us0_rts #13 us1_tx #18 us1_rx #17 us1_clk #16 us1_cs #15 us1_cts #14 us1_rts #13 leu0_tx #18 leu0_rx #17 i2c0_sda #18 i2c0_scl #17 cmu_clk1 #4 prs_ch3 #9 prs_ch4 #1 prs_ch5 #0 prs_ch6 #12 acmp0_o #18 acmp1_o #18 12 pd11 buscy [adc0: aport3ych3 acmp0: aport3ych3 acmp1: aport3ych3 idac0: aport1ych3] busdx [adc0: aport4xch3 acmp0: aport4xch3 acmp1: aport4xch3] tim0_cc0 #19 tim0_cc1 #18 tim0_cc2 #17 tim0_cdti0 #16 tim0_cdti1 #15 tim0_cdti2 #14 tim1_cc0 #19 tim1_cc1 #18 tim1_cc2 #17 tim1_cc3 #16 le- tim0_out0 #19 le- tim0_out1 #18 pcnt0_s0in #19 pcnt0_s1in #18 us0_tx #19 us0_rx #18 us0_clk #17 us0_cs #16 us0_cts #15 us0_rts #14 us1_tx #19 us1_rx #18 us1_clk #17 us1_cs #16 us1_cts #15 us1_rts #14 leu0_tx #19 leu0_rx #18 i2c0_sda #19 i2c0_scl #18 prs_ch3 #10 prs_ch4 #2 prs_ch5 #1 prs_ch6 #13 acmp0_o #19 acmp1_o #19 13 pd12 buscx [adc0: aport3xch4 acmp0: aport3xch4 acmp1: aport3xch4 idac0: aport1xch4] busdy [adc0: aport4ych4 acmp0: aport4ych4 acmp1: aport4ych4] tim0_cc0 #20 tim0_cc1 #19 tim0_cc2 #18 tim0_cdti0 #17 tim0_cdti1 #16 tim0_cdti2 #15 tim1_cc0 #20 tim1_cc1 #19 tim1_cc2 #18 tim1_cc3 #17 le- tim0_out0 #20 le- tim0_out1 #19 pcnt0_s0in #20 pcnt0_s1in #19 us0_tx #20 us0_rx #19 us0_clk #18 us0_cs #17 us0_cts #16 us0_rts #15 us1_tx #20 us1_rx #19 us1_clk #18 us1_cs #17 us1_cts #16 us1_rts #15 leu0_tx #20 leu0_rx #19 i2c0_sda #20 i2c0_scl #19 prs_ch3 #11 prs_ch4 #3 prs_ch5 #2 prs_ch6 #14 acmp0_o #20 acmp1_o #20 14 pd13 buscy [adc0: aport3ych5 acmp0: aport3ych5 acmp1: aport3ych5 idac0: aport1ych5] busdx [adc0: aport4xch5 acmp0: aport4xch5 acmp1: aport4xch5] tim0_cc0 #21 tim0_cc1 #20 tim0_cc2 #19 tim0_cdti0 #18 tim0_cdti1 #17 tim0_cdti2 #16 tim1_cc0 #21 tim1_cc1 #20 tim1_cc2 #19 tim1_cc3 #18 le- tim0_out0 #21 le- tim0_out1 #20 pcnt0_s0in #21 pcnt0_s1in #20 us0_tx #21 us0_rx #20 us0_clk #19 us0_cs #18 us0_cts #17 us0_rts #16 us1_tx #21 us1_rx #20 us1_clk #19 us1_cs #18 us1_cts #17 us1_rts #16 leu0_tx #21 leu0_rx #20 i2c0_sda #21 i2c0_scl #20 prs_ch3 #12 prs_ch4 #4 prs_ch5 #3 prs_ch6 #15 acmp0_o #21 acmp1_o #21 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 58
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 15 pd14 buscx [adc0: aport3xch6 acmp0: aport3xch6 acmp1: aport3xch6 idac0: aport1xch6] busdy [adc0: aport4ych6 acmp0: aport4ych6 acmp1: aport4ych6] tim0_cc0 #22 tim0_cc1 #21 tim0_cc2 #20 tim0_cdti0 #19 tim0_cdti1 #18 tim0_cdti2 #17 tim1_cc0 #22 tim1_cc1 #21 tim1_cc2 #20 tim1_cc3 #19 le- tim0_out0 #22 le- tim0_out1 #21 pcnt0_s0in #22 pcnt0_s1in #21 us0_tx #22 us0_rx #21 us0_clk #20 us0_cs #19 us0_cts #18 us0_rts #17 us1_tx #22 us1_rx #21 us1_clk #20 us1_cs #19 us1_cts #18 us1_rts #17 leu0_tx #22 leu0_rx #21 i2c0_sda #22 i2c0_scl #21 cmu_clk0 #5 prs_ch3 #13 prs_ch4 #5 prs_ch5 #4 prs_ch6 #16 acmp0_o #22 acmp1_o #22 gpio_em4wu4 16 pd15 buscy [adc0: aport3ych7 acmp0: aport3ych7 acmp1: aport3ych7 idac0: aport1ych7] busdx [adc0: aport4xch7 acmp0: aport4xch7 acmp1: aport4xch7] tim0_cc0 #23 tim0_cc1 #22 tim0_cc2 #21 tim0_cdti0 #20 tim0_cdti1 #19 tim0_cdti2 #18 tim1_cc0 #23 tim1_cc1 #22 tim1_cc2 #21 tim1_cc3 #20 le- tim0_out0 #23 le- tim0_out1 #22 pcnt0_s0in #23 pcnt0_s1in #22 us0_tx #23 us0_rx #22 us0_clk #21 us0_cs #20 us0_cts #19 us0_rts #18 us1_tx #23 us1_rx #22 us1_clk #21 us1_cs #20 us1_cts #19 us1_rts #18 leu0_tx #23 leu0_rx #22 i2c0_sda #23 i2c0_scl #22 cmu_clk1 #5 prs_ch3 #14 prs_ch4 #6 prs_ch5 #5 prs_ch6 #17 acmp0_o #23 acmp1_o #23 dbg_swo #2 17 pa0 adc0_extn buscx [adc0: aport3xch8 acmp0: aport3xch8 acmp1: aport3xch8 idac0: aport1xch8] busdy [adc0: aport4ych8 acmp0: aport4ych8 acmp1: aport4ych8] tim0_cc0 #0 tim0_cc1 #31 tim0_cc2 #30 tim0_cdti0 #29 tim0_cdti1 #28 tim0_cdti2 #27 tim1_cc0 #0 tim1_cc1 #31 tim1_cc2 #30 tim1_cc3 #29 le- tim0_out0 #0 le- tim0_out1 #31 pcnt0_s0in #0 pcnt0_s1in #31 us0_tx #0 us0_rx #31 us0_clk #30 us0_cs #29 us0_cts #28 us0_rts #27 us1_tx #0 us1_rx #31 us1_clk #30 us1_cs #29 us1_cts #28 us1_rts #27 leu0_tx #0 leu0_rx #31 i2c0_sda #0 i2c0_scl #31 cmu_clk1 #0 prs_ch6 #0 prs_ch7 #10 prs_ch8 #9 prs_ch9 #8 acmp0_o #0 acmp1_o #0 18 pa1 adc0_extp buscy [adc0: aport3ych9 acmp0: aport3ych9 acmp1: aport3ych9 idac0: aport1ych9] busdx [adc0: aport4xch9 acmp0: aport4xch9 acmp1: aport4xch9] tim0_cc0 #1 tim0_cc1 #0 tim0_cc2 #31 tim0_cdti0 #30 tim0_cdti1 #29 tim0_cdti2 #28 tim1_cc0 #1 tim1_cc1 #0 tim1_cc2 #31 tim1_cc3 #30 le- tim0_out0 #1 le- tim0_out1 #0 pcnt0_s0in #1 pcnt0_s1in #0 us0_tx #1 us0_rx #0 us0_clk #31 us0_cs #30 us0_cts #29 us0_rts #28 us1_tx #1 us1_rx #0 us1_clk #31 us1_cs #30 us1_cts #29 us1_rts #28 leu0_tx #1 leu0_rx #0 i2c0_sda #1 i2c0_scl #0 cmu_clk0 #0 prs_ch6 #1 prs_ch7 #0 prs_ch8 #10 prs_ch9 #9 acmp0_o #1 acmp1_o #1 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 59
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 19 pb11 buscy [adc0: aport3ych27 acmp0: aport3ych27 acmp1: aport3ych27 idac0: aport1ych27] busdx [adc0: aport4xch27 acmp0: aport4xch27 acmp1: aport4xch27] tim0_cc0 #6 tim0_cc1 #5 tim0_cc2 #4 tim0_cdti0 #3 tim0_cdti1 #2 tim0_cdti2 #1 tim1_cc0 #6 tim1_cc1 #5 tim1_cc2 #4 tim1_cc3 #3 le- tim0_out0 #6 le- tim0_out1 #5 pcnt0_s0in #6 pcnt0_s1in #5 us0_tx #6 us0_rx #5 us0_clk #4 us0_cs #3 us0_cts #2 us0_rts #1 us1_tx #6 us1_rx #5 us1_clk #4 us1_cs #3 us1_cts #2 us1_rts #1 leu0_tx #6 leu0_rx #5 i2c0_sda #6 i2c0_scl #5 prs_ch6 #6 prs_ch7 #5 prs_ch8 #4 prs_ch9 #3 acmp0_o #6 acmp1_o #6 20 pb12 buscx [adc0: aport3xch28 acmp0: aport3xch28 acmp1: aport3xch28 idac0: aport1xch28] busdy [adc0: aport4ych28 acmp0: aport4ych28 acmp1: aport4ych28] tim0_cc0 #7 tim0_cc1 #6 tim0_cc2 #5 tim0_cdti0 #4 tim0_cdti1 #3 tim0_cdti2 #2 tim1_cc0 #7 tim1_cc1 #6 tim1_cc2 #5 tim1_cc3 #4 le- tim0_out0 #7 le- tim0_out1 #6 pcnt0_s0in #7 pcnt0_s1in #6 us0_tx #7 us0_rx #6 us0_clk #5 us0_cs #4 us0_cts #3 us0_rts #2 us1_tx #7 us1_rx #6 us1_clk #5 us1_cs #4 us1_cts #3 us1_rts #2 leu0_tx #7 leu0_rx #6 i2c0_sda #7 i2c0_scl #6 prs_ch6 #7 prs_ch7 #6 prs_ch8 #5 prs_ch9 #4 acmp0_o #7 acmp1_o #7 21 pb13 buscy [adc0: aport3ych29 acmp0: aport3ych29 acmp1: aport3ych29 idac0: aport1ych29] busdx [adc0: aport4xch29 acmp0: aport4xch29 acmp1: aport4xch29] tim0_cc0 #8 tim0_cc1 #7 tim0_cc2 #6 tim0_cdti0 #5 tim0_cdti1 #4 tim0_cdti2 #3 tim1_cc0 #8 tim1_cc1 #7 tim1_cc2 #6 tim1_cc3 #5 le- tim0_out0 #8 le- tim0_out1 #7 pcnt0_s0in #8 pcnt0_s1in #7 us0_tx #8 us0_rx #7 us0_clk #6 us0_cs #5 us0_cts #4 us0_rts #3 us1_tx #8 us1_rx #7 us1_clk #6 us1_cs #5 us1_cts #4 us1_rts #3 leu0_tx #8 leu0_rx #7 i2c0_sda #8 i2c0_scl #7 prs_ch6 #8 prs_ch7 #7 prs_ch8 #6 prs_ch9 #5 acmp0_o #8 acmp1_o #8 dbg_swo #1 gpio_em4wu9 22 avdd_0 analog power supply 0. 23 pb14 lfxtal_n buscx [adc0: aport3xch30 acmp0: aport3xch30 acmp1: aport3xch30 idac0: aport1xch30] busdy [adc0: aport4ych30 acmp0: aport4ych30 acmp1: aport4ych30] tim0_cc0 #9 tim0_cc1 #8 tim0_cc2 #7 tim0_cdti0 #6 tim0_cdti1 #5 tim0_cdti2 #4 tim1_cc0 #9 tim1_cc1 #8 tim1_cc2 #7 tim1_cc3 #6 le- tim0_out0 #9 le- tim0_out1 #8 pcnt0_s0in #9 pcnt0_s1in #8 us0_tx #9 us0_rx #8 us0_clk #7 us0_cs #6 us0_cts #5 us0_rts #4 us1_tx #9 us1_rx #8 us1_clk #7 us1_cs #6 us1_cts #5 us1_rts #4 leu0_tx #9 leu0_rx #8 i2c0_sda #9 i2c0_scl #8 cmu_clk1 #1 prs_ch6 #9 prs_ch7 #8 prs_ch8 #7 prs_ch9 #6 acmp0_o #9 acmp1_o #9 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 60
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 24 pb15 lfxtal_p buscy [adc0: aport3ych31 acmp0: aport3ych31 acmp1: aport3ych31 idac0: aport1ych31] busdx [adc0: aport4xch31 acmp0: aport4xch31 acmp1: aport4xch31] tim0_cc0 #10 tim0_cc1 #9 tim0_cc2 #8 tim0_cdti0 #7 tim0_cdti1 #6 tim0_cdti2 #5 tim1_cc0 #10 tim1_cc1 #9 tim1_cc2 #8 tim1_cc3 #7 le- tim0_out0 #10 le- tim0_out1 #9 pcnt0_s0in #10 pcnt0_s1in #9 us0_tx #10 us0_rx #9 us0_clk #8 us0_cs #7 us0_cts #6 us0_rts #5 us1_tx #10 us1_rx #9 us1_clk #8 us1_cs #7 us1_cts #6 us1_rts #5 leu0_tx #10 leu0_rx #9 i2c0_sda #10 i2c0_scl #9 cmu_clk0 #1 prs_ch6 #10 prs_ch7 #9 prs_ch8 #8 prs_ch9 #7 acmp0_o #10 acmp1_o #10 25 dvdd digital power supply. 26 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 27 iovdd digital io power supply. 28 pc7 busay [adc0: aport1ych7 acmp0: aport1ych7 acmp1: aport1ych7] busbx [adc0: aport2xch7 acmp0: aport2xch7 acmp1: aport2xch7] tim0_cc0 #12 tim0_cc1 #11 tim0_cc2 #10 tim0_cdti0 #9 tim0_cdti1 #8 tim0_cdti2 #7 tim1_cc0 #12 tim1_cc1 #11 tim1_cc2 #10 tim1_cc3 #9 le- tim0_out0 #12 le- tim0_out1 #11 pcnt0_s0in #12 pcnt0_s1in #11 us0_tx #12 us0_rx #11 us0_clk #10 us0_cs #9 us0_cts #8 us0_rts #7 us1_tx #12 us1_rx #11 us1_clk #10 us1_cs #9 us1_cts #8 us1_rts #7 leu0_tx #12 leu0_rx #11 i2c0_sda #12 i2c0_scl #11 cmu_clk1 #2 prs_ch0 #9 prs_ch9 #12 prs_ch10 #1 prs_ch11 #0 acmp0_o #12 acmp1_o #12 29 pc8 busax [adc0: aport1xch8 acmp0: aport1xch8 acmp1: aport1xch8] busby [adc0: aport2ych8 acmp0: aport2ych8 acmp1: aport2ych8] tim0_cc0 #13 tim0_cc1 #12 tim0_cc2 #11 tim0_cdti0 #10 tim0_cdti1 #9 tim0_cdti2 #8 tim1_cc0 #13 tim1_cc1 #12 tim1_cc2 #11 tim1_cc3 #10 le- tim0_out0 #13 le- tim0_out1 #12 pcnt0_s0in #13 pcnt0_s1in #12 us0_tx #13 us0_rx #12 us0_clk #11 us0_cs #10 us0_cts #9 us0_rts #8 us1_tx #13 us1_rx #12 us1_clk #11 us1_cs #10 us1_cts #9 us1_rts #8 leu0_tx #13 leu0_rx #12 i2c0_sda #13 i2c0_scl #12 prs_ch0 #10 prs_ch9 #13 prs_ch10 #2 prs_ch11 #1 acmp0_o #13 acmp1_o #13 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 61
qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 30 pc9 busay [adc0: aport1ych9 acmp0: aport1ych9 acmp1: aport1ych9] busbx [adc0: aport2xch9 acmp0: aport2xch9 acmp1: aport2xch9] tim0_cc0 #14 tim0_cc1 #13 tim0_cc2 #12 tim0_cdti0 #11 tim0_cdti1 #10 tim0_cdti2 #9 tim1_cc0 #14 tim1_cc1 #13 tim1_cc2 #12 tim1_cc3 #11 le- tim0_out0 #14 le- tim0_out1 #13 pcnt0_s0in #14 pcnt0_s1in #13 us0_tx #14 us0_rx #13 us0_clk #12 us0_cs #11 us0_cts #10 us0_rts #9 us1_tx #14 us1_rx #13 us1_clk #12 us1_cs #11 us1_cts #10 us1_rts #9 leu0_tx #14 leu0_rx #13 i2c0_sda #14 i2c0_scl #13 prs_ch0 #11 prs_ch9 #14 prs_ch10 #3 prs_ch11 #2 acmp0_o #14 acmp1_o #14 31 pc10 busax [adc0: aport1xch10 acmp0: aport1xch10 acmp1: aport1xch10] busby [adc0: aport2ych10 acmp0: aport2ych10 acmp1: aport2ych10] tim0_cc0 #15 tim0_cc1 #14 tim0_cc2 #13 tim0_cdti0 #12 tim0_cdti1 #11 tim0_cdti2 #10 tim1_cc0 #15 tim1_cc1 #14 tim1_cc2 #13 tim1_cc3 #12 le- tim0_out0 #15 le- tim0_out1 #14 pcnt0_s0in #15 pcnt0_s1in #14 us0_tx #15 us0_rx #14 us0_clk #13 us0_cs #12 us0_cts #11 us0_rts #10 us1_tx #15 us1_rx #14 us1_clk #13 us1_cs #12 us1_cts #11 us1_rts #10 leu0_tx #15 leu0_rx #14 i2c0_sda #15 i2c0_scl #14 cmu_clk1 #3 prs_ch0 #12 prs_ch9 #15 prs_ch10 #4 prs_ch11 #3 acmp0_o #15 acmp1_o #15 gpio_em4wu12 32 pc11 busay [adc0: aport1ych11 acmp0: aport1ych11 acmp1: aport1ych11] busbx [adc0: aport2xch11 acmp0: aport2xch11 acmp1: aport2xch11] tim0_cc0 #16 tim0_cc1 #15 tim0_cc2 #14 tim0_cdti0 #13 tim0_cdti1 #12 tim0_cdti2 #11 tim1_cc0 #16 tim1_cc1 #15 tim1_cc2 #14 tim1_cc3 #13 le- tim0_out0 #16 le- tim0_out1 #15 pcnt0_s0in #16 pcnt0_s1in #15 us0_tx #16 us0_rx #15 us0_clk #14 us0_cs #13 us0_cts #12 us0_rts #11 us1_tx #16 us1_rx #15 us1_clk #14 us1_cs #13 us1_cts #12 us1_rts #11 leu0_tx #16 leu0_rx #15 i2c0_sda #16 i2c0_scl #15 cmu_clk0 #3 prs_ch0 #13 prs_ch9 #16 prs_ch10 #5 prs_ch11 #4 acmp0_o #16 acmp1_o #16 dbg_swo #3 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 62
6.3.1 gpio pinout overview the gpio pins are organized as 16-bit ports indicated by letters a through f, and the individual pins on each port is indicated by a number from 15 down to 0. table 6.6. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a - - - - - - - - - - - - - - pa1 pa0 port b pb15 pb14 pb13 (5v) pb12 (5v) pb11 (5v) - - - - - - - - - - - port c - - - - pc11 (5v) pc10 (5v) pc9 (5v) pc8 (5v) pc7 (5v) - - - - - - - port d pd15 (5v) pd14 (5v) pd13 (5v) pd12 (5v) pd11 (5v) pd10 (5v) pd9 (5v) - - - - - - - - - port e - - - - - - - - - - - - - - - - port f - - - - - - - - - - - pf4 (5v) pf3 (5v) pf2 (5v) pf1 (5v) pf0 (5v) efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 63
6.4 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. the following table shows the name of the alter- nate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 6.7. alternate functionality overview alternate location functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 description acmp0_o 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 analog comparator acmp0, digital out- put. acmp1_o 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 analog comparator acmp1, digital out- put. adc0_extn 0: pa0 analog to digital converter adc0 ex- ternal reference in- put negative pin adc0_extp 0: pa1 analog to digital converter adc0 ex- ternal reference in- put positive pin boot_rx 0: pf1 bootloader rx boot_tx 0: pf0 bootloader tx cmu_clk0 0: pa1 1: pb15 2: pc6 3: pc11 4: pd9 5: pd14 6: pf2 7: pf7 clock management unit, clock output number 0. cmu_clk1 0: pa0 1: pb14 2: pc7 3: pc10 4: pd10 5: pd15 6: pf3 7: pf6 clock management unit, clock output number 1. dbg_swclktck 0: pf0 debug-interface serial wire clock input and jtag test clock. note that this func- tion is enabled to the pin out of reset, and has a built-in pull down. efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 64
alternate location functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 description dbg_swdiotms 0: pf1 debug-interface serial wire data in- put / output and jtag test mode select. note that this func- tion is enabled to the pin out of reset, and has a built-in pull up. dbg_swo 0: pf2 1: pb13 2: pd15 3: pc11 debug-interface serial wire viewer output. note that this func- tion is not enabled after reset, and must be enabled by software to be used. dbg_tdi 0: pf3 debug-interface jtag test data in. note that this func- tion is enabled to pin out of reset, and has a built-in pull up. dbg_tdo 0: pf2 debug-interface jtag test data out. note that this func- tion is enabled to pin out of reset. gpio_em4wu0 0: pf2 pin can be used to wake the system up from em4 gpio_em4wu1 0: pf7 pin can be used to wake the system up from em4 gpio_em4wu4 0: pd14 pin can be used to wake the system up from em4 gpio_em4wu8 0: pa3 pin can be used to wake the system up from em4 gpio_em4wu9 0: pb13 pin can be used to wake the system up from em4 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 65
alternate location functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 description gpio_em4wu12 0: pc10 pin can be used to wake the system up from em4 i2c0_scl 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pc6 11: pc7 12: pc8 13: pc9 14: pc10 15: pc11 16: pd9 17: pd10 18: pd11 19: pd12 20: pd13 21: pd14 22: pd15 23: pf0 24: pf1 25: pf2 26: pf3 27: pf4 28: pf5 29: pf6 30: pf7 31: pa0 i2c0 serial clock line input / output. i2c0_sda 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 i2c0 serial data in- put / output. letim0_out0 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 low energy timer letim0, output channel 0. letim0_out1 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pc6 11: pc7 12: pc8 13: pc9 14: pc10 15: pc11 16: pd9 17: pd10 18: pd11 19: pd12 20: pd13 21: pd14 22: pd15 23: pf0 24: pf1 25: pf2 26: pf3 27: pf4 28: pf5 29: pf6 30: pf7 31: pa0 low energy timer letim0, output channel 1. leu0_rx 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pc6 11: pc7 12: pc8 13: pc9 14: pc10 15: pc11 16: pd9 17: pd10 18: pd11 19: pd12 20: pd13 21: pd14 22: pd15 23: pf0 24: pf1 25: pf2 26: pf3 27: pf4 28: pf5 29: pf6 30: pf7 31: pa0 leuart0 receive input. leu0_tx 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 leuart0 transmit output. also used as receive input in half duplex commu- nication. lfxtal_n 0: pb14 low frequency crystal (typically 32.768 khz) nega- tive pin. also used as an optional ex- ternal clock input pin. lfxtal_p 0: pb15 low frequency crystal (typically 32.768 khz) posi- tive pin. pcnt0_s0in 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 pulse counter pcnt0 input num- ber 0. pcnt0_s1in 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pc6 11: pc7 12: pc8 13: pc9 14: pc10 15: pc11 16: pd9 17: pd10 18: pd11 19: pd12 20: pd13 21: pd14 22: pd15 23: pf0 24: pf1 25: pf2 26: pf3 27: pf4 28: pf5 29: pf6 30: pf7 31: pa0 pulse counter pcnt0 input num- ber 1. prs_ch0 0: pf0 1: pf1 2: pf2 3: pf3 4: pf4 5: pf5 6: pf6 7: pf7 8: pc6 9: pc7 10: pc8 11: pc9 12: pc10 13: pc11 peripheral reflex system prs, chan- nel 0. efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 66
alternate location functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 description prs_ch1 0: pf1 1: pf2 2: pf3 3: pf4 4: pf5 5: pf6 6: pf7 7: pf0 peripheral reflex system prs, chan- nel 1. prs_ch2 0: pf2 1: pf3 2: pf4 3: pf5 4: pf6 5: pf7 6: pf0 7: pf1 peripheral reflex system prs, chan- nel 2. prs_ch3 0: pf3 1: pf4 2: pf5 3: pf6 4: pf7 5: pf0 6: pf1 7: pf2 8: pd9 9: pd10 10: pd11 11: pd12 12: pd13 13: pd14 14: pd15 peripheral reflex system prs, chan- nel 3. prs_ch4 0: pd9 1: pd10 2: pd11 3: pd12 4: pd13 5: pd14 6: pd15 peripheral reflex system prs, chan- nel 4. prs_ch5 0: pd10 1: pd11 2: pd12 3: pd13 4: pd14 5: pd15 6: pd9 peripheral reflex system prs, chan- nel 5. prs_ch6 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pd9 12: pd10 13: pd11 14: pd12 15: pd13 16: pd14 17: pd15 peripheral reflex system prs, chan- nel 6. prs_ch7 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pa0 peripheral reflex system prs, chan- nel 7. prs_ch8 0: pa2 1: pa3 2: pa4 3: pa5 4: pb11 5: pb12 6: pb13 7: pb14 8: pb15 9: pa0 10: pa1 peripheral reflex system prs, chan- nel 8. prs_ch9 0: pa3 1: pa4 2: pa5 3: pb11 4: pb12 5: pb13 6: pb14 7: pb15 8: pa0 9: pa1 10: pa2 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 peripheral reflex system prs, chan- nel 9. prs_ch10 0: pc6 1: pc7 2: pc8 3: pc9 4: pc10 5: pc11 peripheral reflex system prs, chan- nel 10. prs_ch11 0: pc7 1: pc8 2: pc9 3: pc10 4: pc11 5: pc6 peripheral reflex system prs, chan- nel 11. tim0_cc0 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 timer 0 capture compare input / output channel 0. tim0_cc1 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pc6 11: pc7 12: pc8 13: pc9 14: pc10 15: pc11 16: pd9 17: pd10 18: pd11 19: pd12 20: pd13 21: pd14 22: pd15 23: pf0 24: pf1 25: pf2 26: pf3 27: pf4 28: pf5 29: pf6 30: pf7 31: pa0 timer 0 capture compare input / output channel 1. efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 67
alternate location functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 description tim0_cc2 0: pa2 1: pa3 2: pa4 3: pa5 4: pb11 5: pb12 6: pb13 7: pb14 8: pb15 9: pc6 10: pc7 11: pc8 12: pc9 13: pc10 14: pc11 15: pd9 16: pd10 17: pd11 18: pd12 19: pd13 20: pd14 21: pd15 22: pf0 23: pf1 24: pf2 25: pf3 26: pf4 27: pf5 28: pf6 29: pf7 30: pa0 31: pa1 timer 0 capture compare input / output channel 2. tim0_cdti0 0: pa3 1: pa4 2: pa5 3: pb11 4: pb12 5: pb13 6: pb14 7: pb15 8: pc6 9: pc7 10: pc8 11: pc9 12: pc10 13: pc11 14: pd9 15: pd10 16: pd11 17: pd12 18: pd13 19: pd14 20: pd15 21: pf0 22: pf1 23: pf2 24: pf3 25: pf4 26: pf5 27: pf6 28: pf7 29: pa0 30: pa1 31: pa2 timer 0 compli- mentary dead time insertion channel 0. tim0_cdti1 0: pa4 1: pa5 2: pb11 3: pb12 4: pb13 5: pb14 6: pb15 7: pc6 8: pc7 9: pc8 10: pc9 11: pc10 12: pc11 13: pd9 14: pd10 15: pd11 16: pd12 17: pd13 18: pd14 19: pd15 20: pf0 21: pf1 22: pf2 23: pf3 24: pf4 25: pf5 26: pf6 27: pf7 28: pa0 29: pa1 30: pa2 31: pa3 timer 0 compli- mentary dead time insertion channel 1. tim0_cdti2 0: pa5 1: pb11 2: pb12 3: pb13 4: pb14 5: pb15 6: pc6 7: pc7 8: pc8 9: pc9 10: pc10 11: pc11 12: pd9 13: pd10 14: pd11 15: pd12 16: pd13 17: pd14 18: pd15 19: pf0 20: pf1 21: pf2 22: pf3 23: pf4 24: pf5 25: pf6 26: pf7 27: pa0 28: pa1 29: pa2 30: pa3 31: pa4 timer 0 compli- mentary dead time insertion channel 2. tim1_cc0 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 timer 1 capture compare input / output channel 0. tim1_cc1 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pc6 11: pc7 12: pc8 13: pc9 14: pc10 15: pc11 16: pd9 17: pd10 18: pd11 19: pd12 20: pd13 21: pd14 22: pd15 23: pf0 24: pf1 25: pf2 26: pf3 27: pf4 28: pf5 29: pf6 30: pf7 31: pa0 timer 1 capture compare input / output channel 1. tim1_cc2 0: pa2 1: pa3 2: pa4 3: pa5 4: pb11 5: pb12 6: pb13 7: pb14 8: pb15 9: pc6 10: pc7 11: pc8 12: pc9 13: pc10 14: pc11 15: pd9 16: pd10 17: pd11 18: pd12 19: pd13 20: pd14 21: pd15 22: pf0 23: pf1 24: pf2 25: pf3 26: pf4 27: pf5 28: pf6 29: pf7 30: pa0 31: pa1 timer 1 capture compare input / output channel 2. tim1_cc3 0: pa3 1: pa4 2: pa5 3: pb11 4: pb12 5: pb13 6: pb14 7: pb15 8: pc6 9: pc7 10: pc8 11: pc9 12: pc10 13: pc11 14: pd9 15: pd10 16: pd11 17: pd12 18: pd13 19: pd14 20: pd15 21: pf0 22: pf1 23: pf2 24: pf3 25: pf4 26: pf5 27: pf6 28: pf7 29: pa0 30: pa1 31: pa2 timer 1 capture compare input / output channel 3. us0_clk 0: pa2 1: pa3 2: pa4 3: pa5 4: pb11 5: pb12 6: pb13 7: pb14 8: pb15 9: pc6 10: pc7 11: pc8 12: pc9 13: pc10 14: pc11 15: pd9 16: pd10 17: pd11 18: pd12 19: pd13 20: pd14 21: pd15 22: pf0 23: pf1 24: pf2 25: pf3 26: pf4 27: pf5 28: pf6 29: pf7 30: pa0 31: pa1 usart0 clock in- put / output. us0_cs 0: pa3 1: pa4 2: pa5 3: pb11 4: pb12 5: pb13 6: pb14 7: pb15 8: pc6 9: pc7 10: pc8 11: pc9 12: pc10 13: pc11 14: pd9 15: pd10 16: pd11 17: pd12 18: pd13 19: pd14 20: pd15 21: pf0 22: pf1 23: pf2 24: pf3 25: pf4 26: pf5 27: pf6 28: pf7 29: pa0 30: pa1 31: pa2 usart0 chip se- lect input / output. us0_cts 0: pa4 1: pa5 2: pb11 3: pb12 4: pb13 5: pb14 6: pb15 7: pc6 8: pc7 9: pc8 10: pc9 11: pc10 12: pc11 13: pd9 14: pd10 15: pd11 16: pd12 17: pd13 18: pd14 19: pd15 20: pf0 21: pf1 22: pf2 23: pf3 24: pf4 25: pf5 26: pf6 27: pf7 28: pa0 29: pa1 30: pa2 31: pa3 usart0 clear to send hardware flow control input. us0_rts 0: pa5 1: pb11 2: pb12 3: pb13 4: pb14 5: pb15 6: pc6 7: pc7 8: pc8 9: pc9 10: pc10 11: pc11 12: pd9 13: pd10 14: pd11 15: pd12 16: pd13 17: pd14 18: pd15 19: pf0 20: pf1 21: pf2 22: pf3 23: pf4 24: pf5 25: pf6 26: pf7 27: pa0 28: pa1 29: pa2 30: pa3 31: pa4 usart0 request to send hardware flow control output. efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 68
alternate location functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 description us0_rx 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pc6 11: pc7 12: pc8 13: pc9 14: pc10 15: pc11 16: pd9 17: pd10 18: pd11 19: pd12 20: pd13 21: pd14 22: pd15 23: pf0 24: pf1 25: pf2 26: pf3 27: pf4 28: pf5 29: pf6 30: pf7 31: pa0 usart0 asynchro- nous receive. usart0 synchro- nous mode master input / slave out- put (miso). us0_tx 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 usart0 asynchro- nous transmit. al- so used as receive input in half duplex communication. usart0 synchro- nous mode master output / slave in- put (mosi). us1_clk 0: pa2 1: pa3 2: pa4 3: pa5 4: pb11 5: pb12 6: pb13 7: pb14 8: pb15 9: pc6 10: pc7 11: pc8 12: pc9 13: pc10 14: pc11 15: pd9 16: pd10 17: pd11 18: pd12 19: pd13 20: pd14 21: pd15 22: pf0 23: pf1 24: pf2 25: pf3 26: pf4 27: pf5 28: pf6 29: pf7 30: pa0 31: pa1 usart1 clock in- put / output. us1_cs 0: pa3 1: pa4 2: pa5 3: pb11 4: pb12 5: pb13 6: pb14 7: pb15 8: pc6 9: pc7 10: pc8 11: pc9 12: pc10 13: pc11 14: pd9 15: pd10 16: pd11 17: pd12 18: pd13 19: pd14 20: pd15 21: pf0 22: pf1 23: pf2 24: pf3 25: pf4 26: pf5 27: pf6 28: pf7 29: pa0 30: pa1 31: pa2 usart1 chip se- lect input / output. us1_cts 0: pa4 1: pa5 2: pb11 3: pb12 4: pb13 5: pb14 6: pb15 7: pc6 8: pc7 9: pc8 10: pc9 11: pc10 12: pc11 13: pd9 14: pd10 15: pd11 16: pd12 17: pd13 18: pd14 19: pd15 20: pf0 21: pf1 22: pf2 23: pf3 24: pf4 25: pf5 26: pf6 27: pf7 28: pa0 29: pa1 30: pa2 31: pa3 usart1 clear to send hardware flow control input. us1_rts 0: pa5 1: pb11 2: pb12 3: pb13 4: pb14 5: pb15 6: pc6 7: pc7 8: pc8 9: pc9 10: pc10 11: pc11 12: pd9 13: pd10 14: pd11 15: pd12 16: pd13 17: pd14 18: pd15 19: pf0 20: pf1 21: pf2 22: pf3 23: pf4 24: pf5 25: pf6 26: pf7 27: pa0 28: pa1 29: pa2 30: pa3 31: pa4 usart1 request to send hardware flow control output. us1_rx 0: pa1 1: pa2 2: pa3 3: pa4 4: pa5 5: pb11 6: pb12 7: pb13 8: pb14 9: pb15 10: pc6 11: pc7 12: pc8 13: pc9 14: pc10 15: pc11 16: pd9 17: pd10 18: pd11 19: pd12 20: pd13 21: pd14 22: pd15 23: pf0 24: pf1 25: pf2 26: pf3 27: pf4 28: pf5 29: pf6 30: pf7 31: pa0 usart1 asynchro- nous receive. usart1 synchro- nous mode master input / slave out- put (miso). us1_tx 0: pa0 1: pa1 2: pa2 3: pa3 4: pa4 5: pa5 6: pb11 7: pb12 8: pb13 9: pb14 10: pb15 11: pc6 12: pc7 13: pc8 14: pc9 15: pc10 16: pc11 17: pd9 18: pd10 19: pd11 20: pd12 21: pd13 22: pd14 23: pd15 24: pf0 25: pf1 26: pf2 27: pf3 28: pf4 29: pf5 30: pf6 31: pf7 usart1 asynchro- nous transmit. al- so used as receive input in half duplex communication. usart1 synchro- nous mode master output / slave in- put (mosi). efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 69
6.5 analog port (aport) the analog port (aport) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, adcs, and dacs. the aport consists of wires, switches, and control needed to configurably implement the routes. please see the device reference manual for a complete description. efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 70
pc6 busax pc8 pc10 pf0 pf2 pf4 pf6 busby pc7 busay pc9 pc11 pf1 pf3 pf5 pf7 busbx pd10 buscx pd12 pd14 pa0 pa2 pa4 pb12 pb14 busdy pd9 buscy pd11 pd13 pd15 pa1 pa3 pa5 pb11 pb13 pb15 busdx acmp0 1x 1y 2x 2y 3x 3y 4x 4y acmp1 1x 1y 2x 2y 3x 3y 4x 4y adc0 1x 1y 2x 2y 3x 3y 4x 4y idac0 1x 1y figure 6.4. efm32pg1 aport efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 71
table 6.8. aport client map analog module analog module channel shared bus pin acmp0 aport1xch6 busax pc6 aport1xch8 pc8 aport1xch10 pc10 aport1xch16 pf0 aport1xch18 pf2 aport1xch20 pf4 aport1xch22 pf6 acmp0 aport1ych7 busay pc7 aport1ych9 pc9 aport1ych11 pc11 aport1ych17 pf1 aport1ych19 pf3 aport1ych21 pf5 aport1ych23 pf7 acmp0 aport2xch7 busbx pc7 aport2xch9 pc9 aport2xch11 pc11 aport2xch17 pf1 aport2xch19 pf3 aport2xch21 pf5 aport2xch23 pf7 acmp0 aport2ych6 busby pc6 aport2ych8 pc8 aport2ych10 pc10 aport2ych16 pf0 aport2ych18 pf2 aport2ych20 pf4 aport2ych22 pf6 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 72
analog module analog module channel shared bus pin acmp0 aport3xch2 buscx pd10 aport3xch4 pd12 aport3xch6 pd14 aport3xch8 pa0 aport3xch10 pa2 aport3xch12 pa4 aport3xch28 pb12 aport3xch30 pb14 acmp0 aport3ych1 buscy pd9 aport3ych3 pd11 aport3ych5 pd13 aport3ych7 pd15 aport3ych9 pa1 aport3ych11 pa3 aport3ych13 pa5 aport3ych27 pb11 aport3ych29 pb13 aport3ych31 pb15 acmp0 aport4xch1 busdx pd9 aport4xch3 pd11 aport4xch5 pd13 aport4xch7 pd15 aport4xch9 pa1 aport4xch11 pa3 aport4xch13 pa5 aport4xch27 pb11 aport4xch29 pb13 aport4xch31 pb15 acmp0 aport4ych2 busdy pd10 aport4ych4 pd12 aport4ych6 pd14 aport4ych8 pa0 aport4ych10 pa2 aport4ych12 pa4 aport4ych28 pb12 aport4ych30 pb14 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 73
analog module analog module channel shared bus pin acmp1 aport1xch6 busax pc6 aport1xch8 pc8 aport1xch10 pc10 aport1xch16 pf0 aport1xch18 pf2 aport1xch20 pf4 aport1xch22 pf6 acmp1 aport1ych7 busay pc7 aport1ych9 pc9 aport1ych11 pc11 aport1ych17 pf1 aport1ych19 pf3 aport1ych21 pf5 aport1ych23 pf7 acmp1 aport2xch7 busbx pc7 aport2xch9 pc9 aport2xch11 pc11 aport2xch17 pf1 aport2xch19 pf3 aport2xch21 pf5 aport2xch23 pf7 acmp1 aport2ych6 busby pc6 aport2ych8 pc8 aport2ych10 pc10 aport2ych16 pf0 aport2ych18 pf2 aport2ych20 pf4 aport2ych22 pf6 acmp1 aport3xch2 buscx pd10 aport3xch4 pd12 aport3xch6 pd14 aport3xch8 pa0 aport3xch10 pa2 aport3xch12 pa4 aport3xch28 pb12 aport3xch30 pb14 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 74
analog module analog module channel shared bus pin acmp1 aport3ych1 buscy pd9 aport3ych3 pd11 aport3ych5 pd13 aport3ych7 pd15 aport3ych9 pa1 aport3ych11 pa3 aport3ych13 pa5 aport3ych27 pb11 aport3ych29 pb13 aport3ych31 pb15 acmp1 aport4xch1 busdx pd9 aport4xch3 pd11 aport4xch5 pd13 aport4xch7 pd15 aport4xch9 pa1 aport4xch11 pa3 aport4xch13 pa5 aport4xch27 pb11 aport4xch29 pb13 aport4xch31 pb15 acmp1 aport4ych2 busdy pd10 aport4ych4 pd12 aport4ych6 pd14 aport4ych8 pa0 aport4ych10 pa2 aport4ych12 pa4 aport4ych28 pb12 aport4ych30 pb14 adc0 aport1xch6 busax pc6 aport1xch8 pc8 aport1xch10 pc10 aport1xch16 pf0 aport1xch18 pf2 aport1xch20 pf4 aport1xch22 pf6 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 75
analog module analog module channel shared bus pin adc0 aport1ych7 busay pc7 aport1ych9 pc9 aport1ych11 pc11 aport1ych17 pf1 aport1ych19 pf3 aport1ych21 pf5 aport1ych23 pf7 adc0 aport2xch7 busbx pc7 aport2xch9 pc9 aport2xch11 pc11 aport2xch17 pf1 aport2xch19 pf3 aport2xch21 pf5 aport2xch23 pf7 adc0 aport2ych6 busby pc6 aport2ych8 pc8 aport2ych10 pc10 aport2ych16 pf0 aport2ych18 pf2 aport2ych20 pf4 aport2ych22 pf6 adc0 aport3xch2 buscx pd10 aport3xch4 pd12 aport3xch6 pd14 aport3xch8 pa0 aport3xch10 pa2 aport3xch12 pa4 aport3xch28 pb12 aport3xch30 pb14 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 76
analog module analog module channel shared bus pin adc0 aport3ych1 buscy pd9 aport3ych3 pd11 aport3ych5 pd13 aport3ych7 pd15 aport3ych9 pa1 aport3ych11 pa3 aport3ych13 pa5 aport3ych27 pb11 aport3ych29 pb13 aport3ych31 pb15 adc0 aport4xch1 busdx pd9 aport4xch3 pd11 aport4xch5 pd13 aport4xch7 pd15 aport4xch9 pa1 aport4xch11 pa3 aport4xch13 pa5 aport4xch27 pb11 aport4xch29 pb13 aport4xch31 pb15 adc0 aport4ych2 busdy pd10 aport4ych4 pd12 aport4ych6 pd14 aport4ych8 pa0 aport4ych10 pa2 aport4ych12 pa4 aport4ych28 pb12 aport4ych30 pb14 idac0 aport1xch2 buscx pd10 aport1xch4 pd12 aport1xch6 pd14 aport1xch8 pa0 aport1xch10 pa2 aport1xch12 pa4 aport1xch28 pb12 aport1xch30 pb14 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 77
analog module analog module channel shared bus pin idac0 aport1ych1 buscy pd9 aport1ych3 pd11 aport1ych5 pd13 aport1ych7 pd15 aport1ych9 pa1 aport1ych11 pa3 aport1ych13 pa5 aport1ych27 pb11 aport1ych29 pb13 aport1ych31 pb15 efm32pg1 data sheet pin definitions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 78
7. qfn48 package specifications 7.1 qfn48 package dimensions figure 7.1. qfn48 package drawing efm32pg1 data sheet qfn48 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 79
table 7.1. qfn48 package dimensions dimension min typ max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 a3 0.20 ref b 0.18 0.25 0.30 d 6.90 7.00 7.10 e 6.90 7.00 7.10 d2 4.60 4.70 4.80 e2 4.60 4.70 4.80 e 0.50 bsc l 0.30 0.40 0.50 k 0.20 r 0.09 0.14 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vkkd-4. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. efm32pg1 data sheet qfn48 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 80
7.2 qfn48 pcb land pattern figure 7.2. qfn48 pcb land pattern drawing efm32pg1 data sheet qfn48 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 81
table 7.2. qfn48 pcb land pattern dimensions dimension typ s1 6.01 s 6.01 l1 4.70 w1 4.70 e 0.50 w 0.26 l 0.86 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads. 7. a 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad. 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. efm32pg1 data sheet qfn48 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 82
7.3 qfn48 package marking pppppppppp tttttt yyww # efm32 figure 7.3. qfn48 package marking the package marking consists of: ? pppppppppp C the part number designation. ? tttttt C a trace or manufacturing code. the first letter is the device revision. ? yy C the last 2 digits of the assembly year. ? ww C the 2-digit workweek when the device was assembled. ? # C reserved for future use. current value is 0. efm32pg1 data sheet qfn48 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 83
8. qfn32 package specifications 8.1 qfn32 package dimensions figure 8.1. qfn32 package drawing efm32pg1 data sheet qfn32 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 84
table 8.1. qfn32 package dimensions dimension min typ max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 a3 0.20 ref b 0.18 0.25 0.30 d/e 4.90 5.00 5.10 d2/e2 3.40 3.50 3.60 e 0.50 bsc l 0.30 0.40 0.50 k 0.20 r 0.09 0.14 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vkkd-4. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. efm32pg1 data sheet qfn32 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 85
8.2 qfn32 pcb land pattern figure 8.2. qfn32 pcb land pattern drawing efm32pg1 data sheet qfn32 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 86
table 8.2. qfn32 pcb land pattern dimensions dimension typ s1 4.01 s 4.01 l1 3.50 w1 3.50 e 0.50 w 0.26 l 0.86 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads. 7. a 3x3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad. 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. efm32pg1 data sheet qfn32 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 87
8.3 qfn32 package marking pppppppppp tttttt yyww # efm32 figure 8.3. qfn32 package marking the package marking consists of: ? pppppppppp C the part number designation. ? tttttt C a trace or manufacturing code. the first letter is the device revision. ? yy C the last 2 digits of the assembly year. ? ww C the 2-digit workweek when the device was assembled. ? # C reserved for future use. current value is 0. efm32pg1 data sheet qfn32 package specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 88
9. revision history 9.1 revision 0.31 ? engineering samples note added to ordering information table. 9.2 revision 0.3 ? re-formatted ordering information table and opn decoder. ? removed extraneous sections from dc-dc from system overview. ? updated table formatting for electrical specifications. ? updated electrical specifications with latest available data. ? added i2c and usart spi timing tables. ? moved dc-dc graph to typical performance curves. ? updated aport tables and aport references to correct nomenclature. ? updated top marking description. 9.3 revision 0.2 updated ordering table. changed "1.62 v to 3.8 v single power supply" to "1.62 v to 3.8 v power supply" in the feature list. 9.4 revision 0.1 initial release. efm32pg1 data sheet revision history silabs.com | smart. connected. energy-friendly. preliminary rev. 0.31 | 89
table of contents 1. feature list ................................ 1 2. ordering information ............................ 2 3. system overview .............................. 3 3.1 introduction ............................... 3 3.2 power ................................ 4 3.2.1 energy management unit (emu) ....................... 4 3.2.2 dc-dc converter ............................ 4 3.3 general purpose input/output (gpio) ...................... 4 3.4 clocking ................................ 4 3.4.1 clock management unit (cmu) ....................... 4 3.4.2 internal and external oscillators ....................... 4 3.5 counters/timers and pwm ......................... 5 3.5.1 timer/counter (timer) .......................... 5 3.5.2 real time counter and calendar (rtcc) .................... 5 3.5.3 low energy timer (letimer) ........................ 5 3.5.4 ultra low power wake-up timer (cryotimer) ................. 5 3.5.5 pulse counter (pcnt) .......................... 5 3.5.6 watchdog timer (wdog) ......................... 5 3.6 communications and other digital peripherals ................... 5 3.6.1 universal synchronous/asynchronous receiver/transmitter (usart) .......... 5 3.6.2 low energy universal asynchronous receiver/transmitter (leuart) .......... 6 3.6.3 inter-integrated circuit interface (i 2 c) ..................... 6 3.6.4 peripheral reflex system (prs) ....................... 6 3.7 security features ............................. 6 3.7.1 gpcrc (general purpose cyclic redundancy check) ............... 6 3.7.2 crypto accelerator (crypto) ........................ 6 3.8 analog ................................ 6 3.8.1 analog port (aport) .......................... 6 3.8.2 analog comparator (acmp) ........................ 6 3.8.3 analog to digital converter (adc) ...................... 7 3.8.4 digital to analog current converter (idac) ................... 7 3.9 reset management unit (rmu) ........................ 7 3.10 core and memory ............................ 7 3.10.1 processor core ............................ 7 3.10.2 memory system controller (msc) ...................... 7 3.10.3 linked direct memory access controller (ldma) ................. 7 3.11 memory map .............................. 8 3.12 configuration summary .......................... 9 4. electrical specifications .......................... 10 4.1 electrical characteristics .......................... 10 4.1.1 absolute maximum ratings ........................ 10 4.1.2 operating conditions ........................... 11 table of contents 90
4.1.2.1 general operating conditions ....................... 11 4.1.3 dc-dc converter ............................ 12 4.1.4 current consumption ........................... 14 4.1.4.1 current consumption 1.85v without dc/dc .................. 14 4.1.4.2 current consumption 3.3v without dc/dc ................... 15 4.1.4.3 current consumption 3.3v with dc/dc .................... 16 4.1.5 wake up times ............................. 17 4.1.6 brown out detector ........................... 17 4.1.7 oscillators .............................. 18 4.1.7.1 lfxo ............................... 18 4.1.7.2 hfxo ............................... 19 4.1.7.3 lfrco ............................... 19 4.1.7.4 hfrco and auxhfrco ........................ 20 4.1.7.5 ulfrco .............................. 21 4.1.8 flash memory characteristics ........................ 21 4.1.9 gpio ................................ 22 4.1.10 vmon ............................... 23 4.1.11 adc ................................ 24 4.1.12 idac ................................ 26 4.1.13 analog comparator (acmp) ........................ 28 4.1.14 i2c ................................ 30 4.1.15 usart spi ............................. 32 4.2 typical performance curves ......................... 34 5. typical connection diagrams ........................ 35 5.1 power ................................ 35 5.2 other connections ............................ 36 6. pin definitions .............................. 37 6.1 efm32pg1 qfn48 definition ........................ 37 6.1.1 gpio pinout overview .......................... 46 6.2 efm32pg1 qfn32 with dc-dc definition .................... 47 6.2.1 gpio pinout overview .......................... 54 6.3 efm32pg1 qfn32 without dc-dc definition ................... 55 6.3.1 gpio pinout overview .......................... 63 6.4 alternate functionality pinout ........................ 64 6.5 analog port (aport) ........................... 70 7. qfn48 package specifications ........................ 79 7.1 qfn48 package dimensions ......................... 79 7.2 qfn48 pcb land pattern .......................... 81 7.3 qfn48 package marking .......................... 83 8. qfn32 package specifications ........................ 84 8.1 qfn32 package dimensions ......................... 84 8.2 qfn32 pcb land pattern .......................... 86 8.3 qfn32 package marking .......................... 88 table of contents 91
9. revision history ............................. 89 9.1 revision 0.31 .............................. 89 9.2 revision 0.3 .............................. 89 9.3 revision 0.2 .............................. 89 9.4 revision 0.1 .............................. 89 table of contents .............................. 90 table of contents 92
disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory s izes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptio ns herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the in formation supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products must not be used w ithin any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life a nd/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are generally not intended for military applic ations. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc., silicon laboratories, silicon labs, silabs and the silicon labs logo, cmems?, efm, efm32, efr, energ y micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezmac?, ezradio?, ezradiopro?, dspll?, isomodem ?, precision32?, proslic?, siphy?, usbxpress? and others are trademarks or registered trademarks of silicon laboratories inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa simplicity studio one-click access to mcu and wireless tools, documentation, software, source code libraries & more. available for windows, mac and linux! iot portfolio www.silabs.com/iot sw/hw www.silabs.com/simplicity quality www.silabs.com/quality support and community community.silabs.com

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